Commit Graph

1057 Commits

Author SHA1 Message Date
Kyösti Mälkki
3ab6157ede cpu/intel/hyperthreading: Build only for selected models
Implements intel_sibling_init() that is mostly superseded.

Change-Id: I4956493d8c0c6b922343e060d2d2bd0ec20f5bb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55201
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07 21:03:55 +00:00
Kyösti Mälkki
41a2c73b06 cpu/x86: Default to PARALLEL_MP selected
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-07 21:02:54 +00:00
Angel Pons
772c09739e cpu/intel/model_206ax/acpi.c: Do not report P_BLK
IO MWAIT redirection is disabled, which means reads to the P_LVL2 and
P_LVL3 "registers" will never produce any C-state transition requests.

Change-Id: Ibbf7b915a9909d6bc8e784a439df751e11ec5bee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-07 11:36:53 +00:00
Angel Pons
6e7f9d6824 cpu/intel/model_206ax/acpi.c: Do not report P_BLK
IO MWAIT redirection is disabled, which means reads to the P_LVL2 and
P_LVL3 "registers" will never produce any C-state transition requests.
Moreover, the register resource descriptors for all reported C-states
use the FFixedHW address space, not I/O.

Change-Id: I026835dd24d7ac1e1bae2d851e011e1670abaad4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 04:58:34 +00:00
Angel Pons
151d561ddd cpu/intel/haswell/acpi.c: Do not report P_BLK
Even if IO MWAIT redirection were enabled, the base address is wrong.
Moreover, the register resource descriptors for all reported C-states
use the FFixedHW address space, not I/O.

Change-Id: Ic2faaafbe4928994aeeab8098d8e0fb6703d203d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 04:57:46 +00:00
Angel Pons
00c95b13ab cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR
The MSR only needs to be set when IO MWAIT redirection is to be enabled.

Change-Id: Ie856086babe4dadc690f701bd90a7bbac88cb4ad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 04:56:21 +00:00
Arthur Heymans
cdb81500f1 cpu/intel/car/romstage.c: Drop unused function argument
This is a leftover when migrating to C_ENV_BOOTBLOCK

Change-Id: Ibc610cd15448632dc13d87094853d9b981e2679b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-01 05:58:16 +00:00
Rizwan Qureshi
1aa60a95bd src/intel/microcode: Add support for extended signature table
Microcode header supports advertising support for only one CPU
signature and processor flags. If there are multiple processor
families supported by this microcode blob, they are mentioned in
the extended signature table.

Add support to parse the extended processor signature table to
determine if the microcode blob supports the currently running CPU.

BUG=b:182234962
TEST=Booted ADL brya system with a processor whose signature/pf are
in the extended signature table of a microcode patch. Was able to
match and load the patch appropriately.

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I1466caf4a4ba1f9a0214bdde19cce57dd65dacbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-27 06:35:33 +00:00
Kyösti Mälkki
d2b2a18307 Add Kconfig TPM
Defined as TPM1 || TPM2.

Change-Id: I18c26d6991c2ccf782a515a8e90a3eb82b53b0e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-26 12:31:10 +00:00
Arthur Heymans
0d93ca48c0 cpu/intel/fit: Fix top swap fit
The set_ts_fit_ptr makefile target was never a dependency of another
target and therefore not used.

Change-Id: Ie6b20164fce0dc406a28b4c1b9f41a79c68c27d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-25 12:36:47 +00:00
Arthur Heymans
448c9e19c5 cpu/intel/fit: Remove broken ifittool argument
'-t' is not needed when setting the FIT pointer and breaks
it as '-t' needs an argument so the $(TS_OPTIONS) is not properly
decoded.

Change-Id: I61a3ac1eda42e04152a7d10953bfb8407813d0f3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-25 12:35:40 +00:00
Arthur Heymans
749d2d70aa cpu/intel/fit: Make make fit entries depend on fit pointer
Make sure the fit pointer is set up before entries are added.

Change-Id: I285fbb830a52e43cde5e8db9569a64dafb4408df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-25 12:25:44 +00:00
Arthur Heymans
6419cd3335 cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y
This removes the need to include this code separately on each
platform.

Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-18 16:54:21 +00:00
Angel Pons
88dcb3179b src: Retype option API to use unsigned integers
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.

Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-06 14:48:15 +00:00
Tim Wawrzynczak
6fcc46d1a4 cpu/x86/mtrr: Use a Kconfig for reserving MTRRs for OS
Some platforms which have large amounts of RAM and also write-combining
regions may decide to drop the WC regions in favor of the default when
preserving MTRRs for the OS. From a data safety perspective, this is
safe to do, but if, say, the graphics framebuffer is the region that is
changed from WC to UC/WB, then the performance of writing to the
framebuffer will decrease dramatically.

Modern OSes typically use Page Attribute Tables (PAT) to determine the
cacheability on a page level and usually do not touch the MTRRs. Thus,
it is believed to be safe to stop reserving MTRRs for the OS, in
general; PentiumII is the exception here in that OSes that still
support that may still require MTRRs to be available. In any case, if
the OS wants to reprogram all of the MTRRs, it is of course still free
to do so (after consulting the e820 table).

BUG=b:185452338
TEST=Verify MTRR programming on a brya (where `sa_add_dram_resources`
was faked to think it had 32 GiB of DRAM installed) and variable MTRR
map includes a WC entry for the framebuffer (and all the RAM):
MTRR: default type WB/UC MTRR counts: 13/9.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x00003fff80000000 type 6
MTRR: 1 base 0x0000000077000000 mask 0x00003fffff000000 type 0
MTRR: 2 base 0x0000000078000000 mask 0x00003ffff8000000 type 0
MTRR: 3 base 0x0000000090000000 mask 0x00003ffff0000000 type 1
MTRR: 4 base 0x0000000100000000 mask 0x00003fff00000000 type 6
MTRR: 5 base 0x0000000200000000 mask 0x00003ffe00000000 type 6
MTRR: 6 base 0x0000000400000000 mask 0x00003ffc00000000 type 6
MTRR: 7 base 0x0000000800000000 mask 0x00003fff80000000 type 6
MTRR: 8 base 0x000000087fc00000 mask 0x00003fffffc00000 type 0

ADL has 9 variable-range MTRRs, previously 8 of them were used, and
there was no separate entry for the framebuffer, thus leaving the
default MTRR in place of uncached.

Change-Id: I2ae2851248c95fd516627b101ebcb36ec59c29c3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-29 14:51:47 +00:00
Angel Pons
e76f15f4fd src: Replace remaining {get,set}_option() instances
With this change, the type-unsafe {get,set}_option() API functions are
no longer used directly. The old API gets dropped in a follow-up.

Change-Id: Id3f3e172c850d50a7d2f348b1c3736969c73837d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52512
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23 10:13:39 +00:00
Wonkyu Kim
bdfa35315f cpu/intel/common: use lapicid api
Use lapicid api to support both x2apic mode and apic mode

BUG=None
BRANCH=None
TEST=boot to OS and check apic mode
cat /proc/cpuinfo | grep "apicid"

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5ca5b09ae67941adcc07dfafdfe4ba78b0f81009
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51725
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15 10:57:12 +00:00
Angel Pons
7811a45553 cpu/intel/haswell: Use new fixed BAR accessors
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I5fb31f88bbf7c2f1e44924ca2d3169257a9598dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-10 16:04:59 +00:00
Arthur Heymans
c9aecb4440 cpu/intel/fit: Reserve the FIT pointer using a .c file
No need to do this assembly anymore.

Change-Id: I69b42c31e495530fe96030a5a25209775f9d4dca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19 11:23:59 +00:00
Arthur Heymans
eeacd8349c cpu/intel/fit: Add the FIT table as a separate CBFS file
With CBnT a digest needs to be made of the IBB, Initial BootBlock, in
this case the bootblock. After that a pointer to the BPM, Boot Policy
Manifest, containing the IBB digest needs to be added to the FIT
table.

If the fit table is inside the IBB, updating it with a pointer to the
BPM, would make the digest invalid.
The proper solution is to move the FIT table out of the bootblock.

The FIT table itself does not need to be covered by the digest as it
just contains pointers to structures that can by verified by the
hardware itself, such as microcode and ACMs (Authenticated Code
Modules).

Change-Id: I352e11d5f7717147a877be16a87e9ae35ae14856
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50926
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:23:21 +00:00
Furquan Shaikh
f14c05f144 cpu/intel/microcode: Fix caching logic in intel_microcode_find
CB:49896 added support in `intel_microcode_find()` to cache the found
microcode for faster subsequent accesses. This works okay when the
function succeeds in finding the microcode on BSP. However, if for any
reason, `cpu_microcode_blob.bin` does not contain a valid microcode
for the given processor, then the logic ends up attempting to find
microcode again and again every time it is called (because
`ucode_updates` is set to NULL on failed find, thus retriggering the
whole find sequence every time). This leads to a weird race condition
when multiple APs are running in parallel and executing this
function.

A snippet of the issues observed in the scenario described above:
```
...
microcode: Update skipped, already up-to-date
...
Microcode header corrupted!
...

```

1. AP reports that microcode update is being skipped since the current
version matches the version in CBFS (even though there is no matching
microcode update in CBFS).
2. AP reports microcode header is corrupted because it thinks that the
data size reported in the microcode is larger than the file read from
CBFS.

Above issues occur because each time an AP calls
`intel_microcode_find()`, it might end up seeing some intermittent
state of `ucode_updates` and taking incorrect action.

This change fixes this race condition by separating the logic for
finding microcode into an internal function `find_cbfs_microcode()`
and maintaining the caching logic in `intel_microcode_find()` using a
boolean flag `microcode_checked`.

BUG=b:182232187
TEST=Verified that `intel_microcode_find()` no longer makes repeated
attempts to find microcode from CBFS if it failed the first time.

Change-Id: I8600c830ba029e5cb9c0d7e0f1af18d87c61ad3a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51371
Reviewed-by: Patrick Rudolph
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12 17:33:01 +00:00
Angel Pons
e49dec45c8 cpu/intel/haswell: Constify ACPI c-state arrays
Change-Id: I5538d8279392238e59aba99ade4b5fe13f250ca8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49805
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:57:00 +00:00
Angel Pons
618b9ade15 cpu/intel/haswell: Drop c-state table indirection
Accessing it directly allows proper bounds-checking.

Change-Id: Ifb539051e4a91ddcdb5ffec4850dc2fb30482aea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49804
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:54:55 +00:00
Angel Pons
85790d028f cpu/intel/model_206ax: Drop c-state table indirection
Accessing it directly allows proper bounds-checking.

Change-Id: I2582a7edf5fba28febe570bddccacb85a3269684
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:54:48 +00:00
Angel Pons
d8b9e562d0 cpu/intel/model_206ax: Replace generate_cstate_entries
Leverage the existing `acpigen_write_CST_package` function.

Yes, bad devicetree values can trigger undefined behavior. The old code
already had this issue, and will be addressed in subsequent commits.

Change-Id: Icec5431987d91242930efcea0c8ea4e3df3182fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49093
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:54:39 +00:00
Angel Pons
11235d6875 cpu/intel/haswell/acpi.c: Correct get_cores_per_package
CPUID result does not change when HyperThreading is disabled on
HT-enabled CPUs, which breaks `generate_cpu_entries`. Use MSR 0x35
instead, which returns the currently-enabled core and thread count.
Also rename the function to `get_logical_cores_per_package, which is
more accurate. Based on commit 920d2b77f2 (cpu/intel/206ax/acpi.c: Fix
get_cores_per_package). The MSR definition is the same for Sandy Bridge
and Haswell.

Change-Id: I5e1789d3037780b4285c9e367ff0e2b0d4365b39
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49099
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:29:07 +00:00
Elyes HAOUAS
45ce5d8973 src: Remove unused <arch/cpu.h>
Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:25:23 +00:00
Elyes HAOUAS
56a676e5d0 cpu/intel/microcode: Fix typo in function parameter
Change-Id: I9b03105a6808a67c2101917e1822729407271627
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-11 10:19:04 +00:00
Elyes HAOUAS
00b5f53361 treewide [Kconfig]: Remove useless comment
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02 13:49:49 +00:00
Kyösti Mälkki
0b7446a269 sb/intel/i82801gx,ix: Drop MPEN from GNVS
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.

Change-Id: I3928e5973fe65d9a4fe7975e5d5584efe6e5f2f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:54:31 +00:00
Arthur Heymans
9daf5f071c cpu/intel/microcode: Reuse existing function to read MCU revision
Change-Id: If198fa68c0a29f46906151e667d7b00e2a3ab00d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:51:15 +00:00
Patrick Rudolph
3fa23b8c00 soc/intel/*: Get rid of custom microcode caching
Get rid of custom microcode caching in MPinit and SGX code and
use the caching introduced in intel_microcode_find() instead.

Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:46:30 +00:00
Arthur Heymans
93cb1809a2 cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZE
This fixes a regression introduced by
Commit 985821c (cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE)
where the CAR base is not aligned to its size.

Change-Id: If54cb178e86426e1491dda4047302632d876a8f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50029
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 12:34:52 +00:00
Patrick Rudolph
0bea950a47 cpu/intel/microcode: Add caching layer in intel_microcode_find
Cache the found microcode for faster subsequent accesses.

Change-Id: Ic40d57964600f8f20ddb26c7d1691b043fd89f29
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49896
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 09:23:45 +00:00
Frans Hendriks
9d732d3462 cpu/intel/common/fsb.c: Correct code style
lint report warning

Solve the RETURN_VOID

BUG = N/A
TEST = N/A

Change-Id: I3b8088494049b5c3244531a4a77af4153edbdff4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28 09:17:52 +00:00
Kyösti Mälkki
e76ce871c8 arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits
With top-aligned bootblock this is no longer globally needed.
The default maximum is now a generous 256 KiB with couple
platforms having lower limits of 32 KiB and 64 KiB.

Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28 08:55:31 +00:00
Angel Pons
aaa4a0d39e cpu/intel/common/fsb.c: Add Broadwell CPUID models
Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for
both the traditional and ULT variants of Broadwell, because the CPU
driver for Haswell already contains CPUIDs for both Broadwell types.

Without this patch, Broadwell CPUs would hang when trying to print the
first console log message, but only if flashconsole was not enabled.

This was missed in commit f542b7bcef (cpu/intel/haswell: Add Broadwell
CPUIDs and microcode) and went unnoticed until now because the tests
were done with flashconsole enabled, which somehow boots properly even
though the console time tracking would not work (depends on TSC).

Tested on out-of-tree Acer E5-573, fixes booting without flashconsole.

Change-Id: I78a1696771d4d6d2138ec432dc0d8e030f14293b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49939
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26 17:29:20 +00:00
Angel Pons
9f0093d208 cpu/intel/model_2065x: Drop configurable TDP copy-pasta
Configurable TDP is only supported by Ivy Bridge onwards.

Change-Id: I8a742ab6d9d22b325ed725df4f749955efb3028f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24 23:23:43 +00:00
Angel Pons
00d66603db cpu/intel/model_2065x: Drop unused c-state code
None of the mainboards have the magic SpeedStep device, so the C-state
generation function bails out without doing anything. Moreover, this
code is broken and was copied from Sandy Bridge. Thus, drop it.

Change-Id: I580157ee33c599af5fc48b06eeb39cb32c9831ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24 23:23:35 +00:00
Angel Pons
e751a101c0 soc/intel/broadwell: Move romstage.c to Haswell
Broadwell no longer has CPU code.

Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46951
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:04:25 +00:00
Angel Pons
9d733def59 soc/intel/broadwell: Use Haswell CPU headers
Now that the boards use Haswell's CPU code, Broadwell can be updated.

Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46949
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:03:55 +00:00
Angel Pons
f542b7bcef cpu/intel/haswell: Add Broadwell CPUIDs and microcode
Broadwell can now use the Haswell CPU driver.

Change-Id: I36138cab72b1e3ad0ff7f6434996f5ce00de9d0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46942
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:01:24 +00:00
Angel Pons
1c7ba62eb7 cpu/intel/haswell: Set C9/C10 vccmin
Backport commit ab7586fa26 (broadwell: Set C9/C10 vccmin) to Haswell.

Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46922
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:01:09 +00:00
Angel Pons
c86b119495 cpu/intel/haswell: Add fast ramp voltage for Broadwell
Backport commit 55228ba4b4 (broadwell: Changes from 2.2.0 ref code) to
Haswell, to eventually migrate Broadwell to use the same Haswell code.

Change-Id: I03d9ff16bcaab9091bd723ce933aa3f2d71e29b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46921
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:00:59 +00:00
Angel Pons
c89d2a2890 cpu/intel/haswell: Enable timed MWAIT if supported
Broadwell code unconditionally enables timed MWAIT, but not all Haswell
steppings support it. In preparation for merging Haswell and Broadwell,
also enable timed MWAIT on Haswell code, but only if it is supported.

Change-Id: I1d11d62f1801d65ae4d5623994fd55fd35e8f34a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46916
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:25:22 +00:00
Angel Pons
8b0636e06f cpu/intel/haswell: Clean up CPUID definitions
The `mobile` suffix is misleading, since desktop CPUs share the same
CPUIDs. Remove unused stepping IDs and add the full CPUIDs instead.
Finally, add Broadwell CPUIDs in preparation for merging CPU code.
Note that steppings for Haswell in various comments are incorrect.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46915
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 11:27:27 +00:00
Angel Pons
8e6f162cc0 cpu/intel/haswell: Add s0ix support
Backport Broadwell's s0ix support to Haswell in preparation to unify
both platforms' CPU code. Note that only ULT variants support s0ix.

This option is currently unused, but will be put to use in subsequent
commits, when switching Broadwell mainboards to use Haswell's CPU code.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46924
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 11:27:07 +00:00
Elyes HAOUAS
985821c4f2 cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE
Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE".
It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets
should have at least 256K L2 cache. That is plenty for XIP RO cache of
bootblock + romstage and a 32K CAR.

Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-01-21 09:08:14 +00:00
Elyes HAOUAS
398df49d3f cpu/intel/smm/gen1/smmrelocate.c: Remove repeated word
Change-Id: I478f8ab0cf0a4004b4d7294efb330dc800253e4a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:31:06 +00:00
Patrick Georgi
2cc5bcbf7f build system: Always add coreboot.pre dependency to intermediates
They all operate on that file, so just add it globally.

Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15 23:54:09 +00:00