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Author SHA1 Message Date
Boris Mittelberg
130de14a05 arch/x86/acpi: Add code for KEY_MENU 
Support of MENU key (aka hamburger) for Chromebooks with Vivaldi
keyboard

BUG=b:215038215
TEST=manually tested on Anahera device: pressing T13 key opens menu

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I07873dd9385c743a6512408688ec44a5e97219f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61835
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 20:18:41 +00:00
Boris Mittelberg
0c3b7f5411 ec/google/chromeec: Update ec_commands.h 
This change copies ec_commands.h directly from the Chromium OS EC repo,
with the exception of changing the copyright header to SPDX format.
Update to commit hash af9a119

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I1f2a140257d6127fb19bb514bc345466247b7499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-18 20:18:21 +00:00
Fred Reitberger
636a6dedf9 MAINTAINERS: Add myself 
Change-Id: I441369bc47ad4758c2188cb4e0f7e971607f72d5
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-02-18 19:57:44 +00:00
Felix Held
655caa2da0 soc/amd/common/block/psp/Makefile: add fmap_config.h dependency 
Compiling efs_fmap_check.c depends on fmap_config.h already being
generated, so add this dependency.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85e0900574f928d1594f8d1831ba58f959b75d27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2022-02-18 17:14:33 +00:00
Felix Held
63226901c7 soc/amd/common/block/apob/apob_cache: use APOB cache size from FMAP 
Also add the Makefile dependency on the fmap_config.h file to make sure
that this file already exists when it's included.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I540ea2c14fd187845efd3c0c8c1e4b8f82c8cac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2022-02-18 17:14:12 +00:00
Elyes Haouas
14976dbed0 include/acpi/acpi.h: Drop non-existing update_ssdt() 
Change-Id: Ie8535d97e883d3fed9414fb5ba65a0797b989c0d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2022-02-18 17:13:23 +00:00
Elyes Haouas
61c9440888 include/acpi/acpi.h: Drop non-existing update_ssdtx() 
Change-Id: I2fd8470ed2b8e8f00de4ba64258aac1db52744c1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2022-02-18 17:13:08 +00:00
Subrata Banik
ef47212bf8 mb/google/brya/var/{redrix, redrix4es}: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I61f8f39ce7651d499756f4975840f32f89b04ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-18 15:24:23 +00:00
John Su
41994fee94 mb/google/brya/var/felwinter: Update DPTF parameters for Felwinter 
Follow thermal team design to remove TSR3 sensor and update thermal
table for next build. The DPTF parameters were verified by thermal
team.

BUG=b:219690502
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0e34fabe546b6eabb3d3adad583668a15a1d908b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2022-02-18 14:57:44 +00:00
Shon Wang
d91a6842bf mb/google/brya/var/vell: Correct MIPI camera info 
The CIO2 port was incorrectly set to 2, while the correct port is 1

BUG=b:210801553
TEST=Build and boot on vell, camera works correctly now

Change-Id: I53d8448ed0e12777456af9b0bc65a04595b47e37
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61946
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:57:27 +00:00
Subrata Banik
d1275fb886 mb/google/brya/var/volmar: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1e0b51ee4db73bdff79365d4954a3245a430f140
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62051
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:56:55 +00:00
Subrata Banik
5b0ce06d3d mb/google/brya/var/vell: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e4837489d90c2edd7deaa2af0533085f1ff5ae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62049
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:56:45 +00:00
Subrata Banik
d55a08242b mb/google/brya/var/taniks: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id44213c7dd4d0df97a6c57d7f1b9d950baaf0e1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62047
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:56:33 +00:00
Subrata Banik
f04faa149f mb/google/brya/var/{taeko, taeko4es}: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie304b08b0b1bbad5547a0169ea8056d703141391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61830
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:56:15 +00:00
Subrata Banik
b6d522f6c7 mb/google/brya/var/{primus, primus4es}: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1a4bc1aae8e815b882a607432e40caf1066453b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61828
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:55:11 +00:00
Subrata Banik
bf265b456b mb/google/brya/var/kano: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I07cef3b619991afb6337c38a631ee159677d30a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61826
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:54:59 +00:00
Subrata Banik
11fb6a87d7 mb/google/brya/var/{gimble, gimble4es}: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0274f03926d97fc543b98f3fb961580283202806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61825
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:54:52 +00:00
Subrata Banik
159db81b64 mb/google/brya/var/felwinter: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I33e4501fd689d642682891c7f5bc9cb7ca5e331c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61824
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:54:43 +00:00
Subrata Banik
d2133c2ebf mb/google/brya/var/{brya0, brya4es}: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1940246fd88db29054f85c43672adc97dc90fa04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61823
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:54:27 +00:00
Subrata Banik
08ec66dd12 mb/google/brya/var/{anahera, anahera4es}: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3d8a8a7e2b1e490726986139014cdfcf1271c64b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61805
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:54:17 +00:00
Subrata Banik
a55e5b7739 mb/google/brya/var/agah: Use ACPI _PLD macro 
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idb8f30b2d1069aea1d5ce7c5dda7f99de33a7c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61803
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:54:07 +00:00
Subrata Banik
b832955161 acpi: Use ACPI macros to configure USB port _PLD object 
This patch adds two ACPI macros for USB port A and C _PLD object
configuration as:
1. ACPI_PLD_TYPE_A
2. ACPI_PLD_TYPE_C

The configurable parameters are
- Panel, Port is exposed on which face of a panel.
- Horizontal, Horizontal position on the panel where the device
               connection point resides.
- Group
   - Token, Unique numerical value identifying a group.
   - Position, Identifies this device connection point’s position
                 in the group (i.e. 1st, 2nd).

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I245b17019b6d3c5e380c16cb3c9f4edc4dd10cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2022-02-18 14:53:49 +00:00
Subrata Banik
cb6e4926e7 mb/google/brya/var/volmar: Fix PLD group order 
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iddf0727a538f2063cfabbec1f900c488331f33c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-18 14:53:27 +00:00
Subrata Banik
b29d128023 mb/google/brya/var/vell: Fix PLD group order 
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib0d1be34775c5eacf6cd9b0ec400bd42a93c59e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-18 14:53:18 +00:00
Subrata Banik
df533e6911 mb/google/brya/var/taniks: Fix PLD group order 
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia9bc235c257abce2a3cd63cfd1b17ac356267d8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-18 14:53:07 +00:00
Subrata Banik
0724ab1335 mb/google/brya/var/taeko4es: Fix PLD group order 
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic3fbf307bfa42bd377c8f23c1837a6d15cb378e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-18 14:52:58 +00:00
Subrata Banik
782d012590 mb/google/brya/var/{redrix, redrix4es}: Fix PLD group order 
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80d9038d1f41d65201d6bfdb808708f997d71faf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-18 14:52:48 +00:00
Subrata Banik
8c83e3f7fd mb/google/brya/var/{primus, primus4es}: Fix PLD group order 
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic97d48633ef1f246c181046ec32ab81614ba5ceb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2022-02-18 14:52:39 +00:00
Subrata Banik
dc07db0c76 mb/google/brya/var/kano: Fix PLD group order 
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I78734f685672347b06783f834643347a35c59e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-18 14:52:29 +00:00
Subrata Banik
166b35210c mb/google/brya/var/{gimble, gimble4es}: Fix PLD group order 
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4e051b21ca55d25c6fc6cfb529078b18adaab2cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62028
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-18 14:52:15 +00:00
Subrata Banik
5a0432182f mb/google/brya/var/{anahera, anahera4es}: Fix PLD group order 
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0c72a5c5306d63c5fce24bf727704d212d0ad0f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2022-02-18 14:52:05 +00:00
Subrata Banik
895691a783 mb/google/brya/var/agah: Fix PLD group order 
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9cef57bbaf3e3519b7f6a7e3d86979722b598ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-18 14:51:57 +00:00
Jan Dabros
559563aaaa mb/google/guybrush: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP 
Guybrush platforms have I2C3 controller which is shared between PSP and
X86. In order to enable cooperation, PSP acts as an arbitrator. Enable
SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is
binded on the OS side.

With this change in place it is important to use correct kernel version
which has I2C-amdpsp driver [1] enabled. Otherwise, we won't have I2C3
available and thus TPM device available in OS, what may end up as a
serious error - guybrush refuses to boot without access to TPM.

BUG=b:204508404
BRANCH=guybrush
TEST=Build proper kernel and firmware. Run on guybrush and verify TPM
     functionality.

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I9dd94e47e1a02e790427b67adff84de3eb3ee387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61965
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-17 23:14:19 +00:00
Jan Dabros
282d715133 soc/amd/common/block/i2c: Add support for shared TPM_I2C controller 
There are platforms equipped with AMD SoC where I2C3 controller
connected to TPM device is shared between X86 and PSP. In order to
handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends
acquire and release requests to be accepted by PSP. An example of
implementation within Linux kernel is available [1].

There is a need to introduce new ACPI_ID ("AMDI0019") so that dedicated
driver on OS side can bind to it and handle this special setup. Since
PSP takes care of I2C controller power management, we need to remove
PowerResource object from DSDT.

BUG=b:204508404
BRANCH=guybrush

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Iccfc09d8c580d7ab2acb69d26b9c293cf625fb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61863
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-17 23:14:02 +00:00
Fred Reitberger
c17330c1dd mb/amd/chausie: Add EC blob into CBFS 
Add chausie EC blob into CBFS at specified location

Change-Id: I48de08a18054efbda655e1563a539ff2ba7a38a6
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-02-17 23:08:25 +00:00
Ravi Kumar Bokka
ca7c9cc3f2 mb/google/herobrine: Disable fingerprint sensor on CRD devices 
Qualcomm CRD devices do not have a fingerprint sensor so removing the
QUP configuration for it.  This QUP also coincidentally is the same as
the one used for the TPM, so this initially was also causing TPM
communication issues during bootup as the QUP was being reconfigured
during the later stages after QcLib execution.

BUG=b:206581077
BRANCH=None
TEST=Boot to kernel without any CR50 communication errors

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I8d13b67796b70b0b7e9a4721cca0b8a54b2b27c1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61716
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-17 22:43:28 +00:00
Karthikeyan Ramasubramanian
e1d6f5b80d util/spd_tools/spd_gen/lp5: Encode Bank Architecture 
ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or
16B Bank Architectures depending on the speed. This influences SDRAM
Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the
individual SoC advisories.

BUG=b:211510456
TEST=Generate SPDs for Sabrina.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-17 21:43:29 +00:00
Karthikeyan Ramasubramanian
3248db0e5a util/spd_tools/spd_gen/lp5: Encode Optional SDRAM features 
ADL and Sabrina provide different advisories to encode Optional SDRAM
features (byte indices 7 & 9). Encode those bytes as per the respective
advisories.

BUG=b:211510456
TEST=Generate the SPD binaries for Sabrina.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-17 21:43:10 +00:00
Robert Chen
6c4135e636 mb/google/brya/var/vell: Add Wifi SAR for vell 
Add wifi sar for vell

BUG=b:218992598
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage

Change-Id: I74fddd1dbcb7019fd5fe394da291f125f0d4960f
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-17 17:13:27 +00:00
Gaggery Tsai
a7305c19e6 mb/google/brya/var/vell: Correct the DQ mapping 
This patch corrects the DQ mapping and enable ECT. In Vell design,
the DQS is swapped in Mc0.ch1, Mc0.ch3, Mc1.ch0, Mc1.ch1 and Mc1.ch2
but the DQ mappings are not swapped and that causes ECT training
failure.

BUT=b:208719081
TEST=emerge-brya coreboot chromeos-bootimage && ensure the system
     passes ECT training and all the way booting to the OS.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Idd2ad16151f0b2b93b00295b75a66ba65cba23cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-17 17:13:03 +00:00
Elyes Haouas
0ff941dd20 src/soc: Remove space before tab 
Spaces before tabs are not allowed.

Change-Id: I0d2c55c2e0108e59facd92b2e2c0f6c418ef6db0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62055
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-17 17:12:49 +00:00
Elyes Haouas
5b0103f9b5 drivers/intel/usb4/retimer/retimer.c: Remove space before tab 
Spaces before tabs are not allowed.

Change-Id: I1aa8490cb81a77f48d69c16c175eb4fec70dc0db
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62054
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-17 17:12:23 +00:00
Varshit B Pandya
2938c46765 soc/intel/alderlake: Add CNVi common driver Kconfig 
Alder Lake has CNVI device. Select SOC_INTEL_COMMON_BLOCK_CNVI
for Alder Lake.


Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6bf2292e870c990deb63fbf6e841ae7c5c63b3a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-02-17 17:12:09 +00:00
Elyes Haouas
9647e630a0 soc/mediatek/mt8195/include/soc/addressmap.h: Remove space before tab 
Spaces before tabs are not allowed.

Change-Id: I2732c01fd87c56227d47a4c0104de8e227b0cc34
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62018
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-17 17:11:56 +00:00
Felix Held
727a224aed amd/common/block/gpio/gpio: don't use -1 as bitmask in gpio_or32 
The and-mask passed to the gpio_update32 call needs all 32 bits to be
set to ones. When building as 32 bit binary the -1UL will result in the
needed bit mask, but for a 64 bit build the constant would have 64 bits
set to ones which then gets truncated to 32 bits causing a compiler
error. Use 0xffffffff as bit mask instead which behaves correctly in
both cases and also clarifies what this is doing.

TEST=Timeless build for Chausie results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0b6a50bd914fdbb7a78885efb6c610715e2d26c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62053
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-17 15:44:42 +00:00
Felix Held
79313528cd amd/common/block/spi/fch_spi_ctrl: use uintptr_t for addresses 
This fixes a build failure when trying to build the code in 64 bit mode.

TEST=Timeless build for Chausie results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8fe7b626d9d72c0b8ed07ced93e46f795e36848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2022-02-17 15:44:26 +00:00
Shelley Chen
ffc8532869 mb/google/herobrine: Add Gigadevice SPI Part 
BUG=b:182963902
BRANCH=None
TEST=emerge-herobrine coreboot

Change-Id: I73dc695afb7aa2b32aa966070eb057c828073d47
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-02-16 23:42:44 +00:00
Shelley Chen
4ffdd075af mb/google/herobrine: Alphabetize SPI_FLASH configs 
BUG=b:182963902
BRANCH=None
TEST=None

Change-Id: Ia73460d335e859644511b7e9ca80111a919baf2c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-02-16 23:42:35 +00:00
Raul E Rangel
de66e66517 soc/amd/cezanne/psp_verstage/uart: Fix off by 1 error 
We only allow index = {0, 1}. Fix the check.

BUG=b:215599230
TEST=Build guybrush
BRANCH=guybrush

Found-by: Coverity CID 1469611
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I59615ab39faeded43b3803b4450c84ab8a8b81ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61988
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-16 22:08:54 +00:00
Arthur Heymans
fff20212af Use the fallthrough statement in switch loops 
Clang does not seem to work with 'fall through' in comments.

Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-16 21:29:53 +00:00