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Author SHA1 Message Date
Varshit B Pandya
7f7ac206f8 src/driver/intel/mipi_camera: Update ACPI entry to provide silicon info 
CPUID_ALDERLAKE_N_A0 is ES. Add it to generate is_es = 1 in ACPI

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Icc65c52a9dadebe4ebab3d0c30599eb0db38bc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
 2022-02-22 15:58:37 +00:00
Felix Held
cbaf753012 soc/amd/common/block/lpc/espi_util: use __fallthrough 
Using __fallthrough instead of a comment about the fall-through being
intentional should make clang stop complaining about intended fall-
through statements.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
 2022-02-22 15:56:55 +00:00
Felix Held
6f4a5454ac vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependency 
Compiling vboot_check.c depends on fmap_config.h already being generated
so add this dependency.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1fe2b738d76ae16dee3e1ebdca512264303a481c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
 2022-02-22 15:56:03 +00:00
Werner Zeh
6f74d38dc8 mb/siemens/mc_apl2: Enable PCI device for I2C bus 0 
On mc_apl2 the external RTC is connected to I2C bus 3. All other I2C bus
devices (16.0, 16.1 and 16.2) have been disabled as they are not used.
While coreboot can handle the case where a PCI device does not have
function 0 enabled but a later one (here function 3), Linux seems to
check for function 0 first and ignores the rest if function 0
is missing. So enable PCI device 16.0 in order to let Linux use 16.3
again.

Test=Boot into Linux and make sure that PCI device 16.0 and 16.3 are
visible and I2C attached RTC works properly.

Change-Id: I55a748b6de8128f4b26b908118feff9f06d3fb7c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-02-22 15:25:00 +00:00
Felix Singer
88ccd4863c util/nixshell: Add a Nix shell for building documentation 
Add a Nix shell config allowing to build the coreboot documentation.

Change-Id: I1c9715c677342241b78fbdef0afeb4536f48d50f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2022-02-22 10:31:41 +00:00
Elyes Haouas
4045935eb8 include/acpi/acpi.h: Drop non-existing acpi_create_madt_lapic_nmis() 
Change-Id: Ide854e5c8e2ed507548047cb6e1fad49efaffbb8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2022-02-22 00:02:27 +00:00
FrankChu
53d13cbb21 mb/google/volteer/var/drobit: update default codec HID to 10EC5682 
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:204517112
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic37e7e6757476f1d30bea31fcde4deebebd488a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2022-02-21 23:59:41 +00:00
FrankChu
e46e9b04ae mb/google/volteer/var/delbin: update default codec HID to 10EC5682 
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:204523176
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I36e35522aba2463124b7e6e7046b1a56758b534d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2022-02-21 23:59:21 +00:00
FrankChu
994c1910e8 mb/google/volteer/var/copano: update default codec HID to 10EC5682 
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:218245715
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30a1fe2ef8d750616f6907f86a5329f035920504
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2022-02-21 23:58:58 +00:00
Zheng Bao
f08705db4e soc/amd/sabrina/fw.cfg: Change the instance of PMUI/D to 2 
Change-Id: Ie9dbed7d6dd1e5f0c97d4a6cedea3d6bd7b000a2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
 2022-02-21 23:49:35 +00:00
Zheng Bao
e220faa18a amdfwtool: Add entries for PMUI & PMUD with instance 2 
Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
 2022-02-21 23:48:57 +00:00
Zheng Bao
990d154898 amdfwtool: Add support for AMD's BIOS A/B recovery feature 
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
              0x4A -> PSP L2 B -> BIOS L2 B

The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.

To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.

TEST=Majolica(Cezanne)

Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-02-21 23:47:20 +00:00
Zheng Bao
1a9e54302b soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD 
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.

Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-02-21 21:29:50 +00:00
Reka Norman
5bba93e08a mb/google/brya: Enable eMMC HS400 mode for nissa 
Based on the nivviks and nereid schematics, nissa is using eMMC HS400
mode, so enable this in devicetree.

BUG=b:197479026
TEST=Build test nivviks and nereid

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
 2022-02-21 17:05:45 +00:00
Felix Held
aade40c3f6 mb/amd/chausie/chromeos.fmd: resize EC size in FMAP to 4kByte 
Only the info about the location of the EC firmware will be stored right
at the beginning of the flash, so the size can be reduced to 4kByte
which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE
file itself is smaller than this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-21 16:02:41 +00:00
Arthur Heymans
b4389598cf soc/intel/alderlake: Make clang static assert happy 
Change-Id: Ia3cd66f6b735f7430abcdba8a9323d5ee1320fd4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-21 15:30:13 +00:00
Arthur Heymans
141163d5ea drivers/intel/pmc_mux: Fix printing type 
Change-Id: I1cb517323e7d609ae6624363e116e9814fc631cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-02-21 15:29:55 +00:00
Arthur Heymans
02967e6113 soc/intel/alderlake: Fix function pointer type 
const void is not a proper return type for a function. It's the
function pointer themselves that need to be const.

This fixes building with clang.

Change-Id: I99888ab9d9d80f1d6edb33b9f4a3f556f211a6e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-21 15:28:46 +00:00
Arthur Heymans
b53a55930e drivers/intel/fsp2_0/hob: Remove unused variable 
Change-Id: Ie9f4562be9b019d8dd65d4e9040fefbb6834fa03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-02-21 15:28:06 +00:00
Arthur Heymans
138db0601d soc/intel/adl/bootblock/report_platform.c: Use the correct format 
Change-Id: I54c40434f44621c4ea6564ac9c87c5b2fa083b5d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-21 15:27:35 +00:00
Arthur Heymans
4998aaee23 ec/google/chromeec/ec_acpi.c: Cast compatible enum types 
Clang complains about this.

Change-Id: If7af9d5a81c1c381490c9634e3da68ff7f5edda8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-21 15:27:15 +00:00
Elyes Haouas
b55ac09ce3 [acpi]{include,soc/amd,southbridge/amd}: Clarify ARM_boot_arch in comments 
Change-Id: I8b209da90b5a591f62e760961c64c4c63e6ef65b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-02-21 15:26:30 +00:00
Felix Singer
3a5e6f529c util/liveiso: Use programs.flashrom.enable 
NixOS 21.11 introduced the option `programs.flashrom.enable`. The option
allows installing flashrom and hooking up its udev rules. Thus, set it
to `true` and add the user `user` to the `flashrom` group allowing it to
use the programmers.

Change-Id: I017ddb4314702a5252dfc0d05cd1e4961043d23b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2022-02-21 15:25:18 +00:00
Elyes HAOUAS
2164c308b4 include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)' 
'printram(x, ...)' is already defined in 'include/device/dram/common.h' file

Change-Id: I75e19065b9e713df3190202b7ca9e9cd8f3f44a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-02-21 15:23:12 +00:00
Subrata Banik
e0ddea49d1 soc/intel/denverton_ns: Add pmc_mmio_regs as public function 
This patch adds `pmc_mmio_regs` a public function for other IA common
code may need to get access to this function.

BUG=none
TEST=none

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I67a0f7fdcd0827172426bc938569a5022eff16f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2022-02-21 15:22:35 +00:00
Subrata Banik
fac11d000a soc/intel/denverton_ns: Select PMC PCI discoverable config 
This patch selects SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE config to
reflect the SoC actual behaviour where PMC PCI device is still
visible over bus even after FSP-S exit.

Additionally, add DNV PMC PCI ID into PMC IA-common code.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iaaea20e54c909800e4d75b58c29507fc1944cfba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
 2022-02-21 15:22:01 +00:00
John Su
bf81c24e07 mb/google/brya/variants/felwinter: Adjust I2Cs CLK to be around 400 kHz 
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for
audio, TPM, touchscreen, and touchpad.

Audio CLK: 385 kHz
TPM CLK: 380.5 kHz
Touch Screen CLK: 373.3 kHz
Touch Pad CLK: 372.7 kHz

BUG=b:218577918
BRANCH=master
TEST=emerge-brya coreboot chromeos-bootimage
     measure by scope with felwinter.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I3e5cc10d6605f9cc41fa6b31da07a81364b72fe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2022-02-21 15:21:28 +00:00
Fred Reitberger
aa41f77397 mb/amd/chausie/Kconfig: Move EC firmware image in CBFS 
Move the EC to a location that does not conflict with where the main
CBFS is in the chromeos FMAP

Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-21 15:20:47 +00:00
Elyes Haouas
1f5e1b4f3c src/acpi/acpigen.c: Reformat code 
Change-Id: I58851c8a26cad61975f8ba2910eedef3029aab6f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
 2022-02-21 15:19:24 +00:00
Jakub Czapiga
0ac5ed4490 libpayload/vboot: Enable vboot and x86 SHA extension for ChromeOS 
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ia63d44de5440b87cedb35ff92edaa0f35ccd75a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-02-21 15:18:55 +00:00
Jakub Czapiga
b17f1cebcb libpayload/vboot: Add missing quotes enclosing values 
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I1a72ea63a46dedd1fc2e1e53bf7714ad70ebc5e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-02-21 15:18:38 +00:00
Jakub Czapiga
7f663ab3e6 libpayload/vboot/Makefile.inc: Add strip to kconfig-to-binary macro 
Lack of strip made it required to pass arguments to the
kconfig-to-binary macro without spaces. Strip fixed invalid behavior of
this macro.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I9889b45f773b9675fae287086d324c180c505a4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-02-21 15:18:24 +00:00
Krishna Prasad Bhat
dbbb391700 mb/intel/adlrvp_n: Update devicetree 
Update devicetree according to schematics.

TEST=Build and boot Alder Lake N RVP.

Change-Id: I9faee1cb3539a0246fc6a87e15b3150533de1ee5
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
 2022-02-21 15:17:55 +00:00
Krishna Prasad Bhat
a6d642fa8d soc/intel/alderlake: Enable eMMC based on dev enabled 
1. Add eMMC device function in pci_devs.h.
2. Enable eMMC device and configuration based on dev enabled.
3. Add SOC acpi name for eMMC.

Change-Id: I44f17420f7a2a1ca0fbb6cfb1886b1617c5a5064
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-21 15:17:26 +00:00
Krishna Prasad Bhat
d2ca5be61a soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake N 
Alder Lake N SOC has eMMC device. Add ACPI ASL methods for it.

Change-Id: I53f04e81584493049d37b46e078d394d3c8a2f09
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
 2022-02-21 15:17:07 +00:00
Elyes Haouas
8b950f4d7a src/acpi: Add macro for FADT Minor Version and use it 
Change-Id: I6a0e9b33c6a1045a3a4a6717487525b82d41e558
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
 2022-02-21 15:16:37 +00:00
Jakub Czapiga
e904d9ad67 libpayload/cbfs: Add missing new line at the end of error messages 
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ieec281e4f1c67e40976892b3dd1780d2f3802df4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-02-21 15:15:37 +00:00
Felix Singer
d9884d480b Documentation/contributing/gsoc: Use paths to md files 
Replace HTTP links with paths to Markdown files where possible.

Change-Id: I0ecca6460105b10b81c4fc014f00235b5d9b861c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2022-02-21 14:09:18 +00:00
Felix Singer
41dbba9778 Documentation/contributing/gsoc: Fix formatting 
Fix formatting when text should be bold.

Change-Id: I7a88ddc0a56dba8c05d0997f37121d0f2cc84ce6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2022-02-21 14:09:08 +00:00
Elyes HAOUAS
e854b0b5e7 crossgcc: Upgrade CMake to 3.22.2 version 
Change-Id: I4272f72dd6ed686dbad5615a0ab44c8c632b5930
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2022-02-21 08:05:48 +00:00
Felix Singer
05b66147d2 Documentation/contributing: Add GSoC info site 
Add a site containing general information for GSoC contributors and
mentors. It was initially copied from https://www.coreboot.org/GSoC.

Change-Id: I5c21d026118cba571dc6b817e89cc4da296a1799
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
 2022-02-20 04:37:22 +00:00
Felix Held
4ded64c1be mb/amd/chausie: increase RW_MRC_CACHE size in FMAP 
On Sabrina SoCs the size of the APOB has increased, so the size of the
RW_MRC_CACHE FMAP sections needs to be increased in order for the data
to still fit in the corresponding FMAP partition.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-19 00:46:50 +00:00
Cliff Huang
23f33546bb mb/google/brya: remove the delay from for WWAN _ON method. 
Remove unecessary delay in RTD3 _ON Method after PERST# dessartion.

TEST:
2022-02-10T18:22:53.204391Z INFO kernel: [    0.190287] ACPI: Power Resource [RTD3] (on)
2022-02-10T18:22:53.204395Z INFO kernel: [    0.194252] ACPI: Power Resource [RTD3] (off)

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I9bc36af6e6c944fcd3de23b7d49640ad9d25642d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
 2022-02-18 23:23:27 +00:00
Elyes Haouas
a1f5ad0849 nb/amd/pi/00730F01/northbridge.c: Use 'pci_{and,or}_config' 
Change-Id: Ifd77c90fe82e20df91562fccea8b5d89dd4a193d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2022-02-18 23:23:07 +00:00
Subrata Banik
e284ca26bf soc/intel/apollolake: Create alias for GEN_PMCON1 as GEN_PMCON_A 
This patch creates alias for GEN_PMCON_A to maintain parity with other
IA SoC PMC register definitions.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id9a23c58a325cb544c50cbda432fe3117eea22fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-18 20:23:51 +00:00
Subrata Banik
7848aa9335 soc/intel/denverton_ns: Add function to clear PMCON status bits 
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.

Added `MS4V` macro for GEN_PMCON_A bit 18 as per EDS doc:558579.

Additionally, removed `PMC_` prefix from PMC configuration register
macros GEN_PMCON_A/B and ETR3.

Moved PMC PCI device macro from pmc.h to pci_devs.h and name PCH_PMC_DEV
to PCH_DEV_PMC. Also, adjust PCI macros under B0:D31:Fx based on
function numbers.

BUG=b:211954778
TEST=None.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2690ccd387b40c0d89cf133117fd91914e1b71a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-18 20:23:33 +00:00
Subrata Banik
95986169f9 soc/intel/alderlake: Skip FSP Notify APIs 
Alder Lake SoC deselects Kconfigs as below:
- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
to skip FSP notify APIs (Ready to boot and End of Firmware) and make
use of native coreboot driver to perform SoC recommended operations
prior booting to payload/OS.

Additionally, created a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again config.

TODO: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.

BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects required configs.

BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0198c9568de0e74053775682a44324405746389a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-02-18 20:22:58 +00:00
Subrata Banik
90e318bba4 soc/intel/common/cse: Add finalize operation for CSE 
This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware.

BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects all required configs:

BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2022-02-18 20:22:23 +00:00
Subrata Banik
34f26b2989 drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs 
This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_"  prefix.

1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
          USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
          USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
          USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.

For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.

Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.

Additionally, fixed SoC configs inclusion order alphabetically. 

BUG=b:211954778
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-02-18 20:21:45 +00:00
Wisley Chen
03c0853f4d mb/google/brya/redrix{4es}: Disable unused USB2/TCSS ports 
Disable unused USB2/TCSS Ports.

BUG=b:217238553
TEST=FW_NAME=redrix emerge-brya coreboot

Change-Id: I1cdee5b6dc56accb52ba1bf636bdf753a7bfd199
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-02-18 20:18:58 +00:00