We got rid of the dangerous reconfiguration of arbitrary pads in
coreboot, but FSP still overrode that. Make sure that it doesn't
enable a UART for debug output when it isn't configured in core-
boot.
This, again, shows how dangerous it is to leave any FSP UPD at
its binary default.
Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There are only minimal differences between the architecture specific
stdint.h implementations, so let's tidy them up and merge them together
into a single file. In particular,
- Use 'unsigned long' for uintptr_t. This was already the case for x86
and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64
used 'unsigned long long'. This change allows using a single integer
type for uintptr_t across all architectures, and brings it into
consistency with the rest of the code base, which generally uses
'unsigned long' for memory addresses anyway. This change required
fixing several assumptions about integer types in the arm code.
- Use _Bool as the boolean type. This is a specialized boolean type that
was introduced in C99, and is preferrable over hacking booleans
using integers. romcc sadly does not support _Bool, so for that we
stick with the old uint8_t.
- Drop the least and fast integer types. They aren't used
anywhere in the code base and are an unnecessary maintenance burden.
Using the standard fixed width types is essentially always better anyway.
- Drop the UINT64_C() macro. It also isn't used anywhere and doesn't
provide anything that a (uint64_t) cast doesn't.
- Implement the rest of the MIN and MAX numerical limits.
- Use static assertions to check that the integer widths are correct.
Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In patch e29a6ac16a (util/sconfig: Add
commonlib/helpers.h) helpers.h has been added to the include-list.
In headers.h we have a definition for __unused:
On a host system environment where glibc-headers-2.12-1.212 is
installed, a file included by <sys/stat.h> called bits/stat.h have the
following content on line 105 and onwards:
long int __unused[3];
where the mentioned part is part of the structure called struct stat.
If we include commonlib/helpers.h _before_ <sys/stat.h>, the symbol for
__unused will be defined by the preprocessor to be
'__attribute__((unused))', therefore the above mentioned structure member
will be expanded by the preprocessor to be
'long int __attribute__((unused))[3];', which is not a valid C syntax
and therefore produces a compile error for sconfig tool.
To handle this case we need to make sure commonlib/helpers.h is included
_after_ <sys/stat.h>. As the needed part of stat.h (which is
struct stat) is only used in main.c it is safe to move the include from
sconfig.h directly into main.c while taking care of the order.
Change-Id: I9e6960a318d3dd999e1e9c1df326d67094f3b5ce
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It is recommended to never reference PCI busses
using a static number. There is exception with
OPROM execution, where we want to translate the
bus number captured from the actual IO operation
into a matching device node in the devicetree.
Change-Id: I733c645ac5581c000b4cd6cdc05829cd039324d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently some of the LCM ID voltage gaps are below 100mV. For example, the
voltage difference between ID 2 and 3 is 503-440=63mV. To reduce the risk of
misrecognition from the hardware level, the voltages are adjusted so that all
the voltage gaps are larger than 100mV. The RD2 resistor values are also
updated.
BUG=b:136987483
TEST=emerge-kukui coreboot
Change-Id: Ib5c1f927fb54d8c9579f030e42eeec5a27daaceb
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34192
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The tolerance of ADC is +-10mV, but the resistors may also
introduce 1% variation, and causing the final measured
voltage to vary around 5%.
By the advisory from hardware team, checking the tolerance
seems not really solving or helping anything so we should
just ignore that and try to find best matched ID (this
also aligns to what Gru did).
BUG=b:136990271
TEST=Booted on Krane and no longer seeing ADC out of range
BRANCH=None
Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before the system enters S0ix or S3, each GPIO community
will have its dynamic clock gating turned on. Upon return
to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684
BRANCH=none
TEST=Used dut-power to verify that the clock gating is enabled
in S0ix and S3. Also used Store(..., Debug) statements in the
ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Clang Static Analyzer version 8.0.0 detects that the result of
log2_ceil(bios_size) and log2_ceil(window_size) is undefined if the
value of bios_size and window_size are negative. Add negative value
Check for bios_size and window_size after MIN operation.
Change-Id: I28577b6e0ba0ab45bb7804c17ba1f26c4b078b15
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since
it needs to trigger on both edges. With GPIO IRQ, it is necessary to
configure the trigger type in coreboot to match the ACPI
configuration. This is because:
1. ACPI configuration is used by intel-pinctrl driver in Linux kernel
to re-configure the trigger type for the pad in GPIO DW0 config
register. This is done when kernel driver probes and requests irq for
its device.
2. On resume from S3, the pad configuration gets reset and coreboot
sets the trigger type to LEVEL. However, kernel driver does not probe
again. This results in the trigger type being configured incorrectly.
This change updates the GPIO configuration for GPP_H0 to set the same
trigger type as advertised in ACPI for the kernel.
BUG=b:132672011
TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0
works fine on boot as well as after suspend/resume.
Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit b19946cc62 (console: Remove support for printing extra bases)
truncated the digits string to only print integers of up to base 16.
However, that string was also used to print the leading 'x' or 'X' for
hexadecimal integers and is now too short. Fix this to prevent an out
of bounds read.
Change-Id: Iab6470cc88f445f074cf7c0b675346b37f3f2375
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402999
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
These printk() statements were added in commit cdc526e582
(southbridge/nvidia/ck804: Fix boot hang on ASUS KFSN4-DRE w/ K8 CPU)
when debugging another issue. They have undefined reads if ck804_num
is 0 and aren't needed anymore, so drop them.
Change-Id: I80b775370ac6485958948f0bff4510755a6cd2b8
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 137058{1,3}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33459
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check for FSP HOBs is depending on CONFIG_DISPLAY_HOBS.
Use the CONFIG_DISPLAY_HOBS for display HOB info only and always check HOBs.
Use BIOS_ERR of printk() for FSP errors.
BUG=N/A
TEST=Check console output on Facebook FBG1701.
Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
AMD Picasso, and later, will not use CPU_AMD_AGESA or CPU_AMD_PI.
Those two symbols indicate an Arch2008 system. Add SOC_AMD_COMMON
to cause cpu_is_amd() to return TRUE on Picasso.
This removes an error message of "Unknown CPU".
The patch also assumes AMD Family 10h and non-AGESA Family 15h
devices were seeing the "Unknown CPU" message. No functionality
has been verified on these devices.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I3357606c37082f3587ff91924bf7a0e0f8af9625
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34146
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With DEVTREE_EARLY we could create incomplete device
objects with topology links removed to reduce footprint
for bootblock.
Declare everything with 'static __unused DEVTREE_CONST'
to avoid compiler errors and to not expose unusable
device object names to global scope.
Change-Id: Ie4cb9e75f179f44edf4f8256ad8320bc2d4ae71a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Remove unnecessary braces
- Move variable assignment out of function call
- Do not find lowest bit set of 0, which is undefined
- Use unsigned integer when bit shifting
Change-Id: I8651f8cd04165d8d31c44f7919ad5e43499d3d4c
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Only CONFIG_USE_INTEL_FSP_MP_INIT makes a difference whether native MP
init is used or not.
Also make USE_INTEL_FSP_MP_INIT mutually exclusive with
USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI as this option requires
coreboot to set up AP and publish PPI based on it.
Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33357
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
digest from vb2_digest_bufer() does not contains the correct endian.
Create cb_sha_endian() which can convert the calculated digest into big endian
or little endian when required.
BUG=N/A
TEST=Created binary and verify logging on Facebok FBG-1701
Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
