All parameters of DPTC_INPUT() need to be configured on devicetree
when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enabled. The parameters without
configurations on devicetree would be 0 when
SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document
#57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA
and vrm_soc_current_limit_mA on devicetree with thermal table config E
as default table for SMT. Since the dynamic thermal table switching
mechanism is still under cooking, after discussing with thermal team,
suggest adopting config E(limit Soc not reach to max power) as default
thermal config to avoidany thermal-related issue during phase build.
Once the dynamic thermal table switching mechanism is finished, will
change the default value to config A.
BUG=b:258572474, b:248976976, b:259167917, b:257394883
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This patch helps to save 10.200ms of booting time without any issue
seen during MP Init. All cores are out from reset and alive.
Port the Alder Lake 'commit 6526e78967 ("soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL")' also to Meteor Lake.
Additionally, no performance degradation is observed while running
benchmarks.
BUG=b:211770003
TEST=Able to boot Google, Rex to ChromeOS with all cores enabled.
Without this patch:
30:device enumeration 1,480,217 (28,232)
With this patch:
30:device enumeration 1,472,466 (18,334)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iec21470b9b34514169789c39bdc3be4e4ff6c7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69851
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the most part, this just moves the existing post codes into macros
so that they're not just bare numbers.
cache_as_ram.S:
Post code 0x28 was previously pointless with just a single jump between
it and post code 0x29, car_init_done. This code was removed, and the
0x28 value was used to differentiate the car_nem_enhanced subroutine
from the other 0x26 post codes used before calling the clear_car
subroutine.
All other post codes remain identical.
POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas
the POST_SOC codes are expected to be Intel only.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves a lot of post code values, but unifies them between
platforms, so that the same value means the same thing as much as
possible.
The P4-netburst code was the most extensive and most different, so that
dictated the majority of the values. Three were two values there that
didn't match the other files, so those two values, 0x22 & 0x29 have
duplicate entries in the table.
The rest of the entries are similar between platforms, though the values
for many of them were moved to match the P4-netburst values.
POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become
global, while POST_SOC would be specific to the Intel platforms.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69866
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It shouldn't be assumed that all variants of skyrim will use the same
gpio for TPM interrupts.
Use the PSP's new mailbox command to tell it what gpio the tpm interrupt
comes in on.
BUG=b:248193764
TEST=tast run <ip> hwsec.TPMContest
Verify log entry:[DEBUG] PSP: Setting TPM GPIO to 18...OK
Use incorrect GPIO in mailbox cmd and verify TPMContest test
failed.
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69874
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For nissa, the ISH main firmware will be included in the CSE region in
flash instead of loading it from rootfs. So remove the ISH
firmware-name.
BUG=b:234776154
TEST=Boot to OS on nirwen and yaviks UFS SKUs. Check ISH firmware is not
loaded by kernel, and device still goes to S0i3.
Cq-Depend: chrome-internal:5102230
Change-Id: I68f963e17bc0dbf9db9adaaa3f96f06b8737523b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69868
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
CBFS_MCACHE is currently experiencing overflow with CBFS verification
enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB.
This reduction along with the available free space in PSP shared buffer
(32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required
14 KiB.
BUG=b:259342909
TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS
mcache overflows.
FMAP: area COREBOOT found @ 80a000 (8347648 bytes)
VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported
CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes
CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640
VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled
Ensure that firmware_CbfsMcache FAFT test is successful.
Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The patch parses CPU and PCH Trace Hub modes from the debug area in the
Descriptor Region. The modes can be updated in the debug area in order
to configure the CPU and PCH Trace Hub modes. The debug area's offset
starts from the SPI Flash offset:0xf00.
For runtime debugging, the OEM Section in the Descriptor Region is being
used as debug area. The OEM Section details are documented in the SPI
Programmer Guide of CSE Lite kit.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
One register configuring multi-pin functions was outside of the Global
Configuration Registers space and skipped in the initial port patches.
Replicate the vendor configuration and set the Super I/O pin for PECI
functionality.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial CEDT (CXL Early Discovery Table) support based on
CXL spec 2.0 section 9.14.1.
Add functions to create CEDT table (revision 1), and create CEDT
CXL Host Bridge Structure (CHBS) and CXL Fixed Memory Windows
Structure (CFMWS).
TESTED=Create CEDT table on Intel Archer City CRB, dumped the
CEDT table and examined the content.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
There is a note about the default I2C speed of this being 400 kHz
despite the logic in rx6110sa.c sets the fallback (correctly) to
100 kHz.
This information originally comes from the fact the dw_i2c bus
controller default speed is 400 kHz. This is irrelevant to
the default speed of this device as it can be used with any
bus controller.
BUG=none
TEST=coreboot builds correctly (no functional changes).
Change-Id: Ic0ffe5667574c59e1c1df952b84b8a3680b53341
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69545
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After DisplayPort is plugged into type-C port, its hpd signal
instantly presents and EC has mux_info for dp and hpd. This change
fixes the DP detection flow to avoid the 1 second delay while no DP
is connected. If DP is present, there will be requests towards PMC
through the sequence of connect, safe mode, dp and hpd mode.
BUG=b:247670186
TEST=Built image and validated the DisplayPort preboot feature on Rex.
Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Set `EnableTcoTimer=1` in order to keep FSP from
1) enabling ACPI Timer emulation in uCode.
2) disabling the PM ACPI Timer.
Both actions are now done in coreboot.
`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.
Port of commit 0e905801f8 ("soc/intel: transition full control over PM
Timer from FSP to coreboot").
NOTE: This will have a huge power impact when it's enabled. If TCO timer
is disabled, uCode ACPI timer emulation must be enabled, and WDAT table
must not be exposed to the OS.
BUG=none
TEST=Boot to OS on google/rex.
Excerpt from google/rex coreboot log:
[SPEW ] EnableTcoTimer = 1
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch deselects `USE_PM_ACPI_TIMER` kconfig to ensure that
ACPI PM timer remains disabled.
The PM timer (by PMC IP) consumes more power and blocks S0ix so the
timer is emulated by ucode to save power and unblock S0ix.
TEST=Able to boot Google, Rex and ensure PMC MMIO register 0x18fc
BIT 1 is set.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2a23b417ff7fb6328323380a7df46b4b397fc8eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69685
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The coreboot build system automatically adds a `config` file to CBFS
that lists the exact Kconfig configuration that this image was built
with. This is useful to reproduce a build after the fact or to check
whether support for a specific feature is enabled in the image.
However, the file is currently generated using the `savedefconfig`
command to Kconfig, which generates the minimal .config file that is
needed to produce the required config in a coreboot build. This is fine
for reproduction, but bad when you want to check if a certain config was
enabled, since many configs get enabled by default or pulled in through
another config's `select` statement and thus don't show up in the
defconfig.
This patch tries to fix that second use case by instead including the
full .config instead. In order to save some space, we can remove all
comments (e.g. `# CONFIG_XXX is not set`) from the file, which still
makes it easy to test for a specific config (if it's in the file you can
extract the right value, if not you can assume it was set to `n`). We
can also LZMA compress it since this file is never read by firmware
itself and only intended for later re-extraction via cbfstool, which
always has LZMA support included.
On a sample Trogdor device the existing (uncompressed) `config` file
takes up 519 bytes in CBFS, whereas the new (compressed) file after this
patch will take up 1832 bytes -- still a small amount that should
hopefully not break the bank for anyone.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
