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320 Commits

Author SHA1 Message Date
Michał Żygowski
24fba11244 intelblocks/{pmc,p2sb}: Add missing RPL-S PCH IDs for PMC and P2SB 
The PMC and P2SB IDs for Raptor Lake-S PCH were missing. Add them based
on doc 619362 rev 2.2.

Change-Id: I5de00adf2d87cf50571abb02b28e7feebdc3911e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77448
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-15 08:27:33 +00:00
Subrata Banik
525d8d86c3 drivers/wifi: Add PCI ID for Misty Peak WLAN module 
This patch adds support for Intel WIFI-7 series PCIe based WLAN module.

Change-Id: Ia31fdb87e15b50471dc7664e42b1e2625ce1ac58
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-09-05 09:37:16 +00:00
Subrata Banik
d426176e24 drivers/wifi: Avoid camel casing in macro definition 
Convert camel case macros to uppercase and underscore separated macros,
such as:

PCI_DID_CyP_6SERIES_WIFI -> PCI_DID_CP_6SERIES_WIFI
PCI_DID_TyP_6SERIES_WIFI -> PCI_DID_TP_6SERIES_WIFI

This makes the macros more consistent with the rest of the code and
easier to read.

Change-Id: I9c739aab93dc0d043a3c9d9ce799087952c1e20b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77644
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-09-05 09:37:05 +00:00
Tim Crawford
53c6eea2d4 soc/intel/adl: Add Raptor Lake-HX definitions 
Tested by booting System76 Adder WS 3 (addw3) and Serval WS 13 (serw13)
to edk2 payload and then OS.

Ref: Intel Raptor Lake EDS, Volume 1 (#640555, rev. 2.8)
Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-07-14 14:31:24 +00:00
Michał Żygowski
8dc16a9ce2 soc/intel: Replace number in RPL-S ESPI PCI IDs by chipset name 
Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-07-12 13:56:32 +00:00
Michał Żygowski
1aa5caf2ac soc/intel: Fix W790 chipset name 
In newer ADL/RPL PCH EDS 619362 revision 2.1 the ESPI ID 0x7A8A
belongs to the W790 chipset. Earlier revisions had the chipset with
ID 0x7A8A named W685, which was probably just a temporary name.

Change the naming throughout the tree to W790, which is the real
existing chipset.

Change-Id: I87603298d655e9bf898b34acdd5b403f5affaee3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
 2023-07-12 13:55:35 +00:00
Max Fritz
573e6ded9f soc/intel/alderlake: Add support for Raptor Lake S CPUs 
Add PCI IDs, default VR values and power limits for Raptor Lake S
CPUs. Based on docs 639116 and 640555.

TEST=Tested on a MSI PRO Z690-A (ms7d25) with i9-13900K with Ubuntu
22.10 and LinuxBoot (Linux + u-root). Also tested on MSI PRO Z790-P
with i5-13600K (UEFI Payload) usign RPL-S IoT FSP and Ubuntu 22.04.

Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155
Signed-off-by: Max Fritz <antischmock@googlemail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69798
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
 2023-07-12 13:52:16 +00:00
Chia-Ling Hou
b5a032859a soc/intel/jasperlake: Add per-SKU power limits 
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree.

BUG=b:281479111
TEST=emerge-dedede coreboot and read correct value on dibbi

Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Super Ni <super.ni@intel.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
 2023-06-23 15:22:45 +00:00
Jeremy Soller
14d69d03b7 soc/intel/common: Add RPP-S PCI IDs 
Add PCI IDs to support Raptor Point PCH.

Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2)
Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-05-23 20:21:39 +00:00
Pratikkumar Prajapati
0a71e09cf9 soc/intel/common: Add Intel Trace Hub driver 
From Meteor Lake onwards Intel FSP will generate the Trace Hub related
HOB if the Trace Hub is configured to save data in DRAM. This memory
region is used by Trace Hub to store the traces for debugging purpose.
This driver locates the HOB and marks the memory region reserved so
that OS does not use it.

Intel Trace Hub developer manual can be found via document #671536 on
Intel's website.

Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
 2023-03-29 13:15:48 +00:00
Sridhar Siricilla
ebe7f7cee0 soc/intel/{common, meteorlake}: Add support for new MCH 
The patch adds support for new Meteor Lake MCH (ID:0x7d16).

TEST=Build and boot the system having MCH ID:0x7d16.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
 2023-02-10 15:53:43 +00:00
Angel Pons
434d7d4582 sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs 
The desktop 9 series PCHs should be the same as the 8 series PCHs.

Change-Id: Iee93fee4f28b88a72c537944159fb7cbb2796235
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
 2023-02-09 21:40:52 +00:00
Tim Chu
2ccbcc560f soc/intel/cmn/block: Add smbus/p2sb device ids for SPR-SP 
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched
on Jan. 10, 2023. The chipset includes Emmitsburg PCH.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
 2023-01-24 12:48:18 +00:00
Felix Singer
ad6e3c847f tree: Drop Intel Ice Lake support 
Intel Ice Lake is unmaintained and the only user of this platform ever
was the Intel CRB (Customer Reference Board). As it looks like, it was
never ready for production as only engineering sample CPUIDs are
supported.

As announced in the 4.19 release notes, remove support for Intel
Icelake code and move any maintenance on the 4.19 branch.

This affects the following components and their related code:

  * Intel Ice Lake SoC
  * Intel Ice Lake CRB mainboard
  * Documentation

Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-01-19 01:26:36 +00:00
Subrata Banik
3a60e5c827 drivers/intel/ish: Add ADL-P ISH DID 
This patch adds ISH ID for ADL-P to ensure dynamic ASL code is
added into SSDT.

With this patch:
   Scope (\_SB.PCI0.ISHB)
    {
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    }

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48dc6056155824239bb88eda2b0ff5bcd36ced15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71262
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-27 04:41:12 +00:00
Marx Wang
39ede0af15 soc/intel/alderlake: Add Raptor Lake device IDs 
Add system agent ID for RPL QDF#Q2MB/Q2PS

TEST=able to build coreboot successfully

Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-22 18:47:50 +00:00
Kapil Porwal
0dd4494063 soc/intel/cmn/block/cnvi: Add missing CNVI IDs for ADL 
Add missing CNVI IDs for ADL -
ADL-P: 0x51f2, 0x51f3
ADL-S: 0x7af1, 0x7af2, 0x7af3

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I189be9a8c8895a93d98886e6591e771bbce5f564
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
 2022-12-20 15:48:41 +00:00
Kapil Porwal
843699e3cf drivers/wifi: Move ADL-P CNVi IDs from generic to IA common code CNVi driver 
BUG=b:259716145
TEST=Dump SSDT and see that _PRW and _DSD for CNVi device contains
the value from the devicetree on google/redrix.

Before:
    Scope (\_SB.PCI0.WFA3)
    {
        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
        {
            0x6D,
            0x03
        })
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    ...
    }

After:
    Scope (\_SB.PCI0.CNVW)
    {
        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
        {
            0x6D,
            0x03
        })
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    ...
    }

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia4ffedcb53afe350694eb03a144d12f714190cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70447
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 01:31:48 +00:00
Sridhar Siricilla
ce4dc66319 soc/intel/meteorlake: Add Meteor Lake MCH device ID 
Add Meteor Lake MCH device ID 0x7d15.

TEST=Build and verify boot on MTL RVP

With patch, coreboot log:
`[DEBUG]  MCH: device id 7d15 (rev 00) is Meteorlake P`

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-11-18 15:45:56 +00:00
Ravi Sarawadi
33005df7bc soc/intel: Add Meteor Lake IGD device id 0x7d45 
Add new IGD device.

Reference: EDS Vol 1 (640228)

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-15 10:46:21 +00:00
Lawrence Chang
0a5da517c4 soc/intel/alderlake: Add Raptor Lake device IDs 
Add system agent ID for RPL QDF# Q271

TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is
gone

Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com>
Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-10-25 17:35:26 +00:00
Subrata Banik
549c2cd24f device: Drop unused ADL-N UFS PCI Device ID 
This patch drops unused ADL-N UFS PCI Device ID macro
`PCI_DID_INTEL_ADP_UFS`.

BUG=none
TEST=Able to build and boot Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I24e4a1a871763473df4d610b13e8a3a754470233
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
 2022-10-12 23:51:43 +00:00
Meera Ravindranath
ac08e8fa8c mb/google/brya/nivviks: Enable ISH driver and firmware name 
BRANCH=none
BUG=b:234776154
TEST=build and boot Nirwen UFS, copy ISH firmware to host
file system /lib/firmware/intel/adln_ish.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adlnrvp_ish.bin loaded

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I89782b0b7dde1fca0130472a38628e72dfd5c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
 2022-10-11 14:44:06 +00:00
Michał Żygowski
9baffae485 soc/intel/cmn/gfx: Add missing CML-U IGD device IDs 
Intel Core i5-10210U can have the following IGD Device IDs
0x9B21/0x9B41/0x9BAC/0x9BCA/0x9BCC according to Intel ARK. Some of
these IDs were not present in coreboot source nor hooked to the
common graphics driver. Add the missing IDs so that the graphics
driver will probe on the mentioned processor and detect the
framebuffer.

TEST=Boot Protectli VP4650 with i5-10210U and see framebuffer is
detected when using FSP GOP and libgfxinit.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iee720a272367aead31c8c8fa712bade1b6e53948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67975
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-10-06 09:24:54 +00:00
Subrata Banik
a3acac15ee Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver" 
This reverts commit 510a55d4ee.

Reason for revert: Observed `missing read resource` issue for
cnvi device

BUG=b:244687646
TEST=No error seen in AP log while booting Google/rex

Without this patch:
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0
[ERROR]  GENERIC: 0.0 missing read_resources
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0 done

With this patch:
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0 done

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1e881313729f1088cffa7c161722ee79bb9acc49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67566
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-09-16 05:37:05 +00:00
Sean Rhodes
f251660a0e soc/intel/common/smbus: Add missing ID for GLK 
PCI ID taken from Intel doc #569262.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I31d4b7edf3288794c86a6d2b78acdc4cf0ac611f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-08 15:33:35 +00:00
Sean Rhodes
e7bdc1b9e0 soc/intel/commmon/fast_spi: Add missing ID for GLK 
PCI ID taken from Intel doc #569262.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5812e536f3e1c49a272a0b337cc69f3d8f30677f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-08 15:33:20 +00:00
Maximilian Brune
667d0f8966 Fix Alder Lake and Raptor Lake Device ID's 
- ADP_P_* -> RPP_S_* (got mixed up I guess)
- Remove duplicates of ADP_S_ESPI_*
- Add infix _ESPI_ to all ADP_S device ID's

Document: 619362

Change-Id: Ic18ecbd420fc598f0ef6e3cf38e987ac3ae6067e
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66629
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-08-12 17:12:12 +00:00
Maximilian Brune
a0bc90e4ab Add missing ADL-S device identification 
R680E, Q670E, H610E are the ADL-S IoT variants

TEST=Boot ADL-S RVP DDR5 and see silicon info is reported
as PCH: AlderLake-S R680E

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I1804994b4b72f0484eabb15323736679d2668078
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-08-12 17:12:12 +00:00
Wonkyu Kim
25c2075388 soc/intel/common/graphics: Add another Meteor Lake device ID 
Add 0x7d55 as another ID for Meteor Lake graphics controllers.

TEST=Boot with MTL silicon to check coreboot log for DID2
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
 2022-07-07 23:59:37 +00:00
zhixingma
529a64b788 soc/intel: Add Raptor Lake device IDs 
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs.

References:
RaptorLake External Design Specification Volume 1 (640555)
600/700 Series PCH External Design Specification Volume 1 (626817)

BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Booted to OS on adlrvp + rpl silicon

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-28 21:01:27 +00:00
Subrata Banik
88f863cfbb soc/intel: Add Meteor Lake SA device ID 
Add Meteor Lake SA device ID 0x7d14 (4+8, 15W).

BUG=b:224325352
TEST=Able to build MTL SoC and verified SA DID is now shown proper.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-22 17:31:42 +00:00
Michał Żygowski
c8c75fabb3 soc/intel/alderlake/report_platform.c: Add ADL-S identification 
Based on DOC #619501, #619362 and #618427

TEST=Boot MSI PRO Z690-A DDR4 WIFI and see the silicon info is
reported as ADL-S.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8051113515ef63fc4687f53d25140a3f55aadb6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-06-17 14:27:12 +00:00
Subrata Banik
510a55d4ee drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver 
This patch removes the MTL CNVi DIDs macros from IA common code and is
added into the generic wifi driver.

As per Intel Connectivity Platform BIOS Guide, Connectivity Controller
IP for MTL-P is `Magnetar` and supported CRF is `Typhoon Peak 2`.

Previously Garfield Peak DIDs for Alder Lake SoC also added similarly
to generic wifi drivers.

BUG=b:224325352
TEST=Able to build and boot on MTL emulator.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib98762749c71f63df3e8d03be910539469359c68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
 2022-06-03 15:28:12 +00:00
Mario Scheithauer
5b757b597a soc/intel/ehl: Use defines for Ethernet controller IDs 
Use defines for a better reading of the code.

Change-Id: I8e696240d649c0ea2341b8f04b62eebffebc1d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64519
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-05-20 11:22:03 +00:00
Bora Guvendik
f118656736 drivers/wifi/generic: Add new device ID 
New device id 0x51f1 is added.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I695309d529a117bad68fc89a7f136e69cecb95d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-05-16 13:12:51 +00:00
Bora Guvendik
a15b25f6fd soc/intel: Add Raptor Lake device IDs 
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs.

References:
RaptorLake External Design Specification Volume 1 (640555)
600/700 Series PCH External Design Specification Volume 1 (626817)

Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
 2022-05-16 13:12:05 +00:00
Raihow Shi
cb772e54a3 drivers/net/r8168: Add support for Realtek RTL8111K 
The Realtek RT8168 and RTL8111K have a similar programming interface,
therefore add the PCI device ID for the RTL8111K into driver for support.

BUG=b:226253265
TEST=emerge-brask coreboot chromeos-bootimage.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I5ad8f14483393d6f25026847cc0d4229d362bba0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
 2022-03-24 15:47:37 +00:00
Maulik V Vaghela
85a09ef99b soc/intel/adl-n: Add device ID for TCSS XHCI 
This patch adds TCSS XHCI device ID for ADL-N CPU which is required
for USB3 port enumeration.

Document Reference: 645548 revision 1.0 (Chapter 2.3)

BUG=None
BRANCH=None
TEST=Check if device is detected correctly and ACPI entries are
generated for device 0d.0

Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-03-23 14:59:12 +00:00
Wonkyu Kim
9f4010753d soc/intel/common: Include Meteor Lake device IDs 
Reference: chapter2 in Meteor Lake EDS vol1 (640228)

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62581
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-03-09 22:28:33 +00:00
Felix Singer
43b7f41678 src: Make PCI ID define names shorter 
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.

Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'

* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2022-03-07 08:32:09 +00:00
Jon Murphy
6e368f79ec soc/amd/sabrina: Add XHCI configuration 
Add xhci 2 controller support for additional USB port/ Dummy setting

BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-02-28 13:29:24 +00:00
Krishna Prasad Bhat
8d436cfc1a soc/intel/alderlake: Correct Alder Lake M/N ESPI device ID 
Alder Lake M/N ESPI ID 18 was incorrectly assigned to be 0x5482. Assign
it to the correct value.
Reference documents: 619501, 645548.

Change-Id: I08bd218fd128497825b96aa5b9496826afa620d2
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61947
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-02-16 15:38:34 +00:00
Usha P
af5a9d64a5 soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N 
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M
IDs in the current code. Hence rename those device IDs as ADL_M_N and
use them for Alder Lake-N platform.

Document Number: 619501, 645548

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
 2022-02-11 23:55:20 +00:00
Tim Wawrzynczak
c585d8c96c soc/intel/common: Add Crash Log and PMC SRAM PCI device IDs 
Add Alder Lake and Tiger Lake specific Crash Log and PMC SRAM device
IDs.

Document Number: 619501, 645548

Change-Id: I64b58b8c345bd54774c4dab7b65258714cd8dc9e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2022-02-10 12:52:41 +00:00
Kane Chen
3f8bff7764 soc/intel/alderlake: Add Alder Lake P IGD device IDs 
This patch adds additional IGD device IDs as per document 638514.

BUG=b:216420554
TEST=coreboot is able to probe the IGD device during PCI enumeration.

Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-01-31 04:39:13 +00:00
Usha P
8f2df280e1 soc/intel/common: Include Alder Lake-N device IDs 
Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs.
Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548)

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
 2022-01-25 16:10:46 +00:00
Krishna Prasad Bhat
eed82d181b soc/intel/common: Add Alder Lake N eMMC device ID 
Add eMMC device ID for Alder Lake N SOC.
Reference: Alder Lake N Platform EDS Volume 1 (Doc# 645548)

Change-Id: Id35ec2d508bec8ff7d6f1c5fbfaf209d42b25c72
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
 2022-01-18 16:15:06 +00:00
Jeff Daly
2a81cab066 pci_ids.h: Make Denverton IDs consistent with other Intel SoCs 
Align Denverton PCI ID define names with other Intel SoCs. Also,
update the names in SoC code accordingly.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-01-17 15:50:52 +00:00
Felix Held
27b02c2eee include/device/pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoC 
The PCI IDs of the ACP (audio co-processor), the non-GPU HDA audio, the
SMBus and the LPC devices haven't changed from the previous generations
of Zen-based APUs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I41e0a57671b9ef2938b7798d5826de43bea8fe12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2022-01-12 00:44:37 +00:00