Remove unused cannonlake dptf.asl file and cleanup defines from apollolake
dptf.asl file as per soc/intel/common/acpi code changes for dptf.
BUG=None
BRANCH=None
TEST=Build and boot on the system
Change-Id: I4c8bf2bd5da9d5881e7690bff34816b19dd96072
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit d5f1e0f973.
Reason for revert: FSP-S is now fixed to not touch the SPI
configuration registers. Thus, coreboot does not need to reconfigure
SPI after FSP-S has run.
BUG=b:153506142
TEST=Verified that SPI configuration registers look the same before
and after FSP-S has run. em100 works fine without any additional
changes in coreboot to reconfigure SPI.
Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If a UCSI event comes in when the EC is in S0ix mode then the kernel
driver attempts a transaction but fails and this can leave the system
in an unexpected state where the only wake source is the power button.
This change will not notify the UCSI driver if the EC is in S0ix mode
and instead keep track of the event and send it on resume.
BUG=b:157923800
TEST=tested on drallion system:
1. Put drallion system into suspend
2. Attach power supply
3. Ensure the system can wake with keypress
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I43acb089385d9b41ac955f053e409daad67423f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Temporary workaround for S0ix issues related to FSP's handling of 0 value.
When IomTypeCPortPadCfg is 0 FSP completely skips any flow related to this
value which seems to be causing issues with s0ix.
This is still being debugged and a final solution will be made when available
BUG=b:159151238
TEST=flash image with workaround to volteer and verify that s0ix
cycles correctly.
Change-Id: Id79dd1c49958389cdb666b3760abd821bc1973a8
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42268
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change includes uart.c in bootblock, romstage, ramstage and
verstage unconditionally because this file is handling more than just
the UART console configuration. This allows boards to take advantage
of picasso_uart_mmio_ops even if PICASSO_UART is not selected.
uart_platform_base and uart_platform_refclk mustn't be provided if
PICASSO_UART is unset, so add an #if around those functions.
BUG=b:158346697
TEST=Mandolin builds again.
Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for enabling/disabling PCIe hot-plug via
a chip config option PcieRpHotPlug, which is copied to the corresponding
FSP-S UPD.
BUG=b:156879564
BRANCH=none
TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFL defaults for VR TDC config and provide Iccmax for additional Xeon
CPUs tested on the Prodrive/Hermes board.
Based on the following Intel documents:
* Document Number 570805 (XEON E EDS Vol 1)
* Document Number 337344 (CFL Datasheet Vol 1)
* Document Number 571264 (CFL CNP PDG)
Change-Id: I681de076318fb647c44cc8b8c42eb297018cc540
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
When Linux is booted, the kernel reports
"do_IRQ: 1.55 No irq handler for vector"
So far it comes with payloads SeaBIOS and depthcharge, not with
Grub. We assume Grub does something to avoid this problem.
AMD bug tracker system (JIRA PLAT-21393) says the APs can not be set
EXTINT delivery mode.
In Intel 64 and IA-32 Architectures Software Developer’s Manual volume
3A, see chapter 10.5.1 Local Vector Table, it says:
"The APIC architecture supports only one ExtINT source in a system,
usually contained in the compatibility bridge. Only one processor in the
system should have an LVT entry configured to use the ExtINT delivery
mode."
Tested on mandolin (Picasso) board, the error in dmesg is gone.
The bug 153677727 has two parts.
1. Soft lockup
2. do_IRQ 1.55.
The soft lockup issued has been fixed by
https://review.coreboot.org/c/coreboot/+/41128
BUG=b:153677727
TEST=mandolin
Change-Id: I2956dcaad87cc1466deeca703748de33390b7603
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42219
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The call made at mp_ops.post_mp_init() generally
uses four different names. Unify these with followups.
smm_southbridge_enable(SMI_EVENTS)
smm_southbridge_enable_smi()
hudson_enable_smi_generation()
enable_smi_generation()
Furthermore, some platforms do not enable power button
SMI early. It may be preferred to delay the enablement,
but fow now provide global_smi_enable_no_pwrbtn() too.
Change-Id: I6a28883ff9c563289b0e8199cd2ceb9acd6bacda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
LGA775 CPUs can have at most 4 threads, and Eaglelake supports them.
As this socket is also used by other chipsets, temporarily place this
symbol into the northbridge scope until all chipsets are factored out.
Change-Id: I6e01363d995e135815cc70779e0cd5baf806cf60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor. With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.
As a generalization, remove all-y for CONFIG_ARCH_xx guarded
makefiles.
BUG=b:158124527
TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia7dcfed699ee1c0cd5a5250431c5f05bf6d8b9c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add the AMD supplied code (modified to work with GCC) to the vendorcode
directory. Verstage will be running on the PSP as a userspace
application under the bootloader, which is what bl_uapp signifies.
AMD is still working on documentation for the entire PSP userspace
application interface.
BUG=b:158124527
TEST=Build & boot psp_verstage on Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie740c89afe2277eff279fc5c94f88ffd43a78a37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
