Files
system76-coreboot/src
Wonkyu Kim c66c15334a soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD
This patch adds support for enabling/disabling PCIe hot-plug via
a chip config option PcieRpHotPlug, which is copied to the corresponding
FSP-S UPD.

BUG=b:156879564
BRANCH=none
TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:18:45 +00:00
..
2020-06-10 12:53:08 +00:00
2020-06-16 08:01:55 +00:00