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47962 Commits

Author SHA1 Message Date
Jeremy Compostella
1eff77bc59 arch/x86: Reduce max phys address size for Intel TME capable SoCs 
On Intel SoCs, if TME is supported, TME key ID bits are reserved and
should be subtracted from the maximum physical addresses available.

BUG=288978352
TEST=Verified that DMAR ACPI table `Host Address Width` field on rex
     went from 45 to 41.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-12 08:12:02 +00:00
Jeremy Compostella
a6a5b25ce4 cpu/intel: Move is_tme_supported() from soc/intel to cpu/intel 
It makes the detection of this feature accessible without the
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency.

BUG=288978352
TEST=compilation

Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-12 08:11:17 +00:00
Elyes Haouas
e099176412 mb/packardbell: Remove space between function name and '(' 
Change-Id: Ied86fb05a3930f1bd900d106b5f3c79466a81a6d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 21:39:45 +00:00
Elyes Haouas
c54a967147 soc/intel: Remove space between function name and '(' 
Change-Id: I1dbfca33c437c680118eb3a92e60b5607c93e565
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77768
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-11 21:39:08 +00:00
Elyes Haouas
d3bb087360 mb/lenovo: Remove space between function name and '(' 
Change-Id: I9b1e3ad668c332bebdaf48a2e95f1f9e2131d598
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 21:38:13 +00:00
Elyes Haouas
fb39a2f91a mb/google: Remove space between function name and '(' 
Change-Id: I0909f24844fab3dfc859ea8c5325344a9872799f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 21:35:10 +00:00
Elyes Haouas
b024e23cfd arch/arm64: Remove space between function name and '(' 
Change-Id: I0cba99070f251d86679c068bb737c05178f4a7c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77771
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-11 21:31:16 +00:00
Elyes Haouas
a4c74578ec soc/cavium: Remove space between function name and '(' 
Change-Id: I25e3cf15a77cf61a60bd31519eae019742842389
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 15:57:58 +00:00
Elyes Haouas
0f3075ea63 sb/intel: Remove space between function name and '(' 
Change-Id: I2e8eb3632c93b4449f108cb690f9bfd8e1ea3776
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77767
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-11 15:57:35 +00:00
Elyes Haouas
9d450b2248 nb/intel: Remove space between function name and '(' 
Change-Id: Ibffaf86f9e32d747c8f2f7a3643df8935fb00047
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 15:52:56 +00:00
Elyes Haouas
98a9b34854 soc/nvidia: Remove space between function name and '(' 
Change-Id: I5b0cdb7b8484080db6571d70ddef145bbaf2e87d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77769
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-11 15:51:44 +00:00
Elyes Haouas
78d2469f05 drivers: Remove space between function name and '(' 
Change-Id: I42e995952a72a23a5f3aeadf428ad13f25546854
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 15:51:04 +00:00
Elyes Haouas
dc75d3e6c1 security/intel/stm: Remove __attribute__(()) 
Change-Id: Id35a0a589128ea2dfb2f0e5873d4fa087b0886a9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-09 04:45:57 +00:00
Elyes Haouas
2dc5c6e2cc soc/amd/common: Remove __attribute__(()) 
Change-Id: I2866dcdd6900c98310b4b3736b40ebe4eaa77ea2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77719
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-09 04:45:33 +00:00
Elyes Haouas
25a7af18a5 drivers/net/ne2k: Remove space before semicolon 
Also move the semicolon on next line.

Change-Id: I68412407ec8c8f99c15f39b0ec08d4fb33eb1b3f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-09 04:44:44 +00:00
Jon Murphy
cbe975d8d8 vendorcode/eltan/security: update attribute use 
Update the use of __attribute__((weak)) to the preferred __weak

BUG=None
TEST=Builds
BRANCH=None

Change-Id: I75a0e7c03e537be2d38b7f9c6b81eafbb5fb8018
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-08 15:22:44 +00:00
Jonathon Hall
89709da1fc mb/purism/librem_cnl: Enable HDMI1 output for Mini native graphics init 
Enable HDMI1 output, which corresponds to the physical DisplayPort
connector, so passive adapters to DVI or HDMI will work with native
graphics init.

Change-Id: I95a147978697f4af092fe61ceacd2e725155d489
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2023-09-08 12:47:08 +00:00
Cliff Huang
cb362cf2bb mb/google/rex: Fix ACPI MPTS method for non-5G board SKUs 
MPTS method should only be generated for the board sku with 5G.

BUG=NA
TEST=Check kernel messages when going to S3. The following errors
should not be seen:
ACPI BIOS Error (bug):
	Could not resolve symbol [\_SB.PCI0.RP06.RTD3._STA]
ACPI Error:
	Aborting method \_SB.MPTS due to previous error (AE_NOT_FOUND)
ACPI Error:
	Aborting method \_PTS due to previous error (AE_NOT_FOUND)

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I78f434c9049773cf5229d3a1f3934ae82d1fe46d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77690
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-08 12:46:45 +00:00
Sean Rhodes
9796d4ce4f mb/starlabs/starbook/rpl: Enable the PD interrupt GPIO 
Enable the PD interrupt GPIO, GPP_B11, so that HPD works when
Thunderbolt is disabled.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie37976d58921b7a12dff16d93d7ac9bdd92edbea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-08 12:45:35 +00:00
Sean Rhodes
1e0d0a721e mb/starlabs/starbook/rpl: Correct GPP_A19 
A19 was incorrectly labelled as TCP0 HPD. It is not connected
so configure it accordingly.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5aea723c2e8c0758d413bbc4bfd0ce92b22d0c87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-08 12:45:15 +00:00
Sean Rhodes
59453aa763 mb/starlabs/starbook/{adl,rpl}: Remove unnecessary entries 
Certain devices are enabled in Alder Lakes chipset.cb, so remove
them from the devicetree.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-08 12:44:54 +00:00
Subrata Banik
3ff6b2ff9e mb/google/rex: Require VBOOT_LID_SWITCH for Chromebook design 
This patch ensures that platforms with lids, such as Chromebooks, only
select the VBOOT_LID_SWITCH configuration option.

Only samples the LID GPIO if VBOOT_LID_SWITCH config is enabled,
otherwise fake LID is open to avoid shutdown after reaching
depthcharge.

Tested by building and booting Google/Rex with the VBOOT_LID_SWITCH
configuration option enabled, and verifying that google/ovis does not
required VBOOT_LID_SWITCH config.

Change-Id: Ic5123b822a5a7021023319cb08a3f9e5225961ba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77693
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-09-08 09:21:35 +00:00
Felix Singer
79503ef515 vc/intel/fsp2/alderlake_n: Drop unused header files 
Change-Id: I870fa65ff05cf5907d62b3af1b2f9c4334b62603
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77260
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-08 02:46:01 +00:00
Felix Singer
1e889d8082 soc/intel/alderlake_n: Hook up the FSP repository 
Change-Id: I57b54653bd29a728825210403c8f426eb1c9cc48
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2023-09-08 02:45:53 +00:00
Martin Roth
74f18777a2 arch to drivers/intel: Fix misspellings & capitalization issues 
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-08 00:53:57 +00:00
Elyes Haouas
cef239675b drivers/pc80/vga/vga_io: Remove unnecessary parentheses 
Parentheses are not required.

Change-Id: Iad1f766a3eb569af39030e43365e8a0a609f5944
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77706
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-07 17:35:38 +00:00
Elyes Haouas
db3e16e73c security/intel: Remove unnecessary blank line after '{' 
Change-Id: I0d2a9c30d332b16efd548433a54f974067bd281e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-07 17:35:19 +00:00
Elyes Haouas
19b4e6487f drivers/siemens/nc_fpga/nc_fpga: Remove space before '++' 
Change-Id: I6ff11df45ddc396391efd651f9938e04646dc0d3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77707
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-09-07 17:34:53 +00:00
Elyes Haouas
ad0b3fa83d ec/lenovo/h8/h8.c: Use sizeof() 
Use 'sizeof(ecfw)' instead of 'sizeof ecfw'.
sizeof operator should only be used for types and variables require sizeof().

Change-Id: Ifae1680917bb0ce610e6ba753741aae233a71103
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-09-07 17:34:22 +00:00
Matt DeVillier
7542ab94df mb/google/myst: Set i2c2 to hidden in devicetree 
Allows ACPI SSDT generator to hide the device from Windows via _STA

Change-Id: I41fc7f847ef08138cb0f430bfd1a170f209163f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77681
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-07 15:59:03 +00:00
Matt DeVillier
5445d4c021 mb/google/zork: Set i2c3 to hidden in devicetree 
Allows ACPI SSDT generator to hide the device from Windows via _STA

Change-Id: I19f0a5a72ec409b306be7bc4bb53425870fc6298
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2023-09-07 15:58:44 +00:00
Matt DeVillier
6695256e69 mb/google/skyrim: Set i2c3 to hidden in devicetree 
Allows ACPI SSDT generator to hide the device from Windows via _STA

Change-Id: Idb5d2cd6eca2a2746e89a371005332e9f621df83
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77675
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-07 15:13:37 +00:00
Matt DeVillier
ea8b45e840 mb/google/guybrush: Set i2c3 to hidden in devicetree 
Allows ACPI SSDT generator to hide the device from Windows via _STA

Change-Id: I22b3ccc2c89a3f7ababd0eaf4e35604880aa0ce7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2023-09-07 15:13:27 +00:00
Tyler Wang
b60f7ead81 mb/google/nissa/var/craask: Modify SD_CARD element to prevent confuse 
Modify SD_CARD element "SD_GL9750S" to "SD_PRESENT" to prevent
confusion.

Origin: 0 --> SD_GL9750S
Modify: 0 --> SD_PRESENT

BUG=b:296505165
TEST=emerge-nissa coreboot

Change-Id: Ic355b7df9f9added4489a764f774851f2e4451c3
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
 2023-09-07 13:38:35 +00:00
Subrata Banik
2527e3f7ed soc/intel/meteorlake: Update LidStatus UPD dynamically 
This patch ensures that the LidStatus UPD is passed a dynamic value,
rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0
devices.

Problem statement:
* FSP-S GFX PEIM initializes the on-board display (eDP) even when the
  LID is physically closed, because LidStatus is always set to 1.
* FSP-S skips external display initialization even when the LID is
  closed.

Solution:
* FSP-S GFX PEIM module understands the presence of an external display
  if LidStatus is not set, and tries to probe the other display
  endpoint.
* Statically passing LidStatus as always enabled (aka 1) does not
  illustrate the exact device scenarios, so this patch updates
  LidStatus dynamically by reading the EC memory map offset.

BUG=b:299137940
TEST=Able to build and boot google/rex to redirect the display
using external HDMI monitor while LID is closed.

Change-Id: I7d7b678227a6c8e32114de069af8455b8c1aa058
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-07 13:37:41 +00:00
Tyler Wang
e352ea1ccd mb/google/rex/var/karis: Update MIPI User facing camera settings 
Update overridetree and GPIO settings for MIPI UFC due to updated
schematic updates.

BUG=b:298133153
TEST=emerge-rex coreboot

Change-Id: I4c3197e3f15e0cb3fc640b1749d8681299981563
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77591
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eran Mitrani <mitrani@google.com>
 2023-09-07 13:35:26 +00:00
Wisley Chen
15cb0d5527 mb/google/brya/var/{kano,osiris,taeko}: Add null pointer check 
Without part no. in CBI, mainboard_get_dram_part_num returns null.
To prevent passing this null pointer to strcmp and avoid unexpected
behavior, proper handling is necessary.

BUG=none
TEST=emerge-brya coreboot

Change-Id: I47e42376c6b1347c56afaec218aed63c5469f0aa
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77646
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-07 13:31:33 +00:00
Robert Chen
d99fac1949 mb/google/brya/var/yavilla: Add VBT data file 
Add data.vbt file for yavilla recovery image. Select INTEL_GMA_HAVE_VBT
for yavilla which currently have a VBT file.

BUG=b:298320552
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I72f98181b3487f8ae9acf6e0f2382a0204f7989c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-07 13:30:23 +00:00
Matt DeVillier
0cd2a50727 device/pci_rom: rename pci_rom_acpi_fill_vfct() 
Rename pci_rom_acpi_fill_vfct() to ati_rom_acpi_fill_vfct() to make
it clear that the function is only used for AMD/ATI VGA option ROMs.

Change-Id: I0e310dd2d7a0432918861632e09a23e162082ea5
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77634
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-06 22:07:50 +00:00
Matt DeVillier
7c04d0e6fd device/pci_rom: Set VBIOS checksum when filling VFCT table 
AMD's Windows display drivers validate the checksum of the VBIOS data
in the VFCT table (which gets modified by the FSP GOP driver), so
ensure it is set correctly after copying the VBIOS into the table if the
FSP GOP driver was run. Without the correct checksum, the Windows GPU
drivers will fail to load with a code 43 error in Device Manager.

Thanks to coolstar for root causing the issue.

TEST=build/boot Win11 on google/skyrim (frostflow), ensure GPU driver
loaded and functional.

Change-Id: I809f87865fd2a25fb106444574b619746aec068d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2023-09-06 22:07:38 +00:00
Felix Held
bfd85218a7 soc/amd: correctly report I2C controller state in ACPI 
Instead of reporting all I2C controllers in the system as enabled in the
corresponding ACPI device's _STA method, report the I2C devices that are
disabled in the devicetree as disabled in the corresponding _STA method
too. This is done by returning the contents of the STAT variable inside
each device's scope in the DSDT that have a default value of 0 (device
not present/disabled). For all enabled and hidden I2C devices
i2c_acpi_fill_ssdt gets called which then writes 0xf (device enabled and
visible) or 0xb (device enabled, but hidden) to the STAT name inside the
same scope, but in the SSDT. This object in the SSDT will then override
the default in the DSDT resulting in the _STA method returning the
correct status of each device. The code was inspired by
commit 7cf9c74518 ("soc/amd/*: Fix UART ACPI device status").

TEST=On Mandolin all I2C controllers are disabled and with this patch
none shows up in the Windows 10 device manager. When enabling an I2C
controller in the devicetree for testing, it shows up again in the
Windows device manager.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4cd9f447ded3a7f0b092218410c89767ec517417
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2023-09-06 19:51:26 +00:00
Elyes Haouas
feb683d1b9 soc/intel/common/block/acpi: Change __attribute__((weak)) to __weak 
Change-Id: I9ecd81ffaa48dbed225a23900704b259569cb7c8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77527
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-06 13:27:52 +00:00
Alexis Savery
8ba64cd608 google/puff: Enable ASPM of RTL8111H 
With kernel 5.15, puff hangs during power idle tests because
the NIC does not enter ASPM L1.2. We add "enable_aspm_l1_2" in
devicetree for RTL8111H to enable ASPM L1.2.

BUG=b:268859220, b:279618219
TEST=emerge and run power.Idle

Change-Id: I129dfd79e8112191453be513b2e3a260429b3030
Signed-off-by: Alexis Savery <asavery@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77570
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-06 13:17:34 +00:00
Alexis Savery
0d3745b67c google/puff: remove workaround that toggled the #ISOLATE pin 
A workaround was added for puff to assert/deassert the #ISOLATE pin
during suspend/resume to resolve the situation where the realtek
ethernet device cannot enter L1.2 mode when its ASPM is disabled.
The realtek driver has since been fixed and ASPM of realtek devices have
been enabled on kernel 5.10 and 5.15 and this original workaround
is now causing suspend/resume errors on kernel 5.15:
r8169 0000:01:00.0: Unable to change power state from D3cold to D0,
device inaccessible

Puff devices were originally shipped with kernel 4.19, and applying
this change to the firmware on a device running 4.19 causes
suspend/resume failures, basically reversing the problem. We are
upreving the puff kernel to 5.15 so we need this patch, but since
it is incompatible with 4.19 we will have to take that into
consideration when pushing new firmware and potentially will need
to backport the necessary fixes to 4.19.

BUG=b:268859220
TEST=suspend_stress_test -c 500 on wyvern

Change-Id: I5eead2d70cd9528b3ca3fadd11f98c0330601324
Signed-off-by: Alexis Savery <asavery@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77378
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
 2023-09-06 13:17:11 +00:00
Wisley Chen
184329c77a mb/google/nissa/yaviks: Disable V1P05 control pin 
Yaviks already disabled external V1P05, so disable V1P05 control pin
which controls the VCC_V1P105_EXT_1P05.

BUG=b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I4128cfcfa5be0d141f0173e87518407331d79e8e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77645
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-06 01:57:27 +00:00
Matt DeVillier
f8beac6b7a soc/amd/common/vboot: Drop reporting of Silicon level 
Per the PSP team, this field in the transfer buffer isn't used anymore
and always set to zero, causing devices to incorrectly report having
pre-production silicon.

Change-Id: Ida4bf4b9328ac83d905e4c3f822e6ceabe9be79d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77630
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2023-09-05 14:39:27 +00:00
Shon Wang
6b69af8f77 mb/google/nissa/var/yavilla: Disable SUSCLK based on fw_config 
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage.
SAR_ID_0 : Yaviks_Gfp2
SAR_ID_1 : Yaviks & Yavilla_MT7921
SAR_ID_2 : Yahiko_Gfp2
SAR_ID_3 : Yavilla_MT7922

BUG=b:298138654
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I2f191683d0623aa5dce815998a24fddce2a36b2c
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77559
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-05 12:49:31 +00:00
Zheng Bao
730c3ba6d8 amdfwtool: Add FW type FUSE_CHAIN in the config file 
We don't have file for the fuse chain, but we need to set the level
for some cases.

Change-Id: Idb546f761ae10b0d19a9879a9a644b788828d523
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
 2023-09-05 12:30:16 +00:00
Johannes Hahn
5a87c82428 mb/siemens/fa_ehl: Process LPDDR4 SPD files and add MT53E512M32D1NP SPD 
The board uses soldered down LPDDR4, so process their SPD files, and add
the SPD for Micron MT53E512M32D1NP-046WTB provided by Micron.

Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I978b7450b106b86eef322df8b33df41e038599eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77349
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
 2023-09-05 12:26:49 +00:00
Wisley Chen
7dccc596f0 mb/google/nissa/var/yaviks: Disable AUX pins based on FW_CONFIG 
Configure the AUX pins as NC based on the FW_CONFIG setting when
the C1 port is not present.

BUG=b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I24fb8f16c2e3b05edf1056b5687ae5ea28c022c0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-05 12:26:20 +00:00