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376dc82dca8be3c1cec3e317d2d175efa690d436
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13 Commits

Author SHA1 Message Date
Richard Spiegel
376dc82dca amd/stoneyridge: Create new name/IRQ association 
Table intr_types[] is hard to maintain, and has unused spaces filled with
NULL. A new table format is needed that creates strong association between
the APIC register index and the associated IRQ name, is easy to maintain
and has no unused space (index) to indicate that a particular register is
unused while still indicating which registers are valid.

Also, the string that defines the name of associated IRQ should be declared
with "#define" in a header, but must be physically initiated in a source
file. The "#define" must make a strong association between the used register
index and the associated IRQ name. Example:
#define INDEX_0X16_NAME "PerMon\t"

BUG=b:69868534
TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh
Processors definitions for Pci_Intr_Index. Also, check for new output
format to confirm write_pci_int_table() is working as desired. There's
no test for write_pci_cfg_irqs, as it's not being used by kahlee.

Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-12-07 02:31:45 +00:00
Richard Spiegel
bec44f22a4 amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c 
In preparation to deleting early_setup,c, transfer all functions except
those related to wide IO to southbridge.c.

BUG=b:64033893
TEST=Build and boot to OS.

Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-12-04 22:27:03 +00:00
Marshall Dawson
91b80416b7 amd/stoneyridge: Enable SMI trap on SlpTyp 
Program PMx08 to support SMIs when software writes the SlpTyp bit in
the Pm1Control register.  The southbridge needs to send the SMI message
prior to the completion response of the I/O cycle.  Also, disable
sending the STPCLK message before the completion response.

Disable the SlpTyp functionality, then enable the SMI source.

BUG=b:65595850

Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-11-17 17:40:51 +00:00
Marshall Dawson
5e2e74f981 amd/stoneyridge: Replace BIT(n) in southbridge 
Use more descriptive #define values for the ACPI features and
register decoding.

Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22427
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2017-11-14 17:17:06 +00:00
Marshall Dawson
f9592ccef0 amd/stoneyridge: Use the new generic acpi_sleep_from_pm1 
Unhardcode the acpi_get_sleep_type() function and rely on the new
function in arch/acpi.h.

Change-Id: Icd49c44fae43effb9f082db354abd327cad9f1ad
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
 2017-11-10 19:16:32 +00:00
Richard Spiegel
cd04e31c8b soc/amd/stoneyridge: Simplify and fix SMBUS code 
Solve issues left from Change-Id Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c
call functions within smbus.c.

Fix some functions that wrongly use SMBHSTCTRL as the register for the
data being transfered. The correct register is SMBHSTDAT0.

Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c.

BUG=b:62200225

Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
 2017-11-10 19:11:12 +00:00
Marshall Dawson
a05fdcb269 amd/stoneyridge: Change SMM setup functions 
Remove the APMC-specific initialization call.  Make the function
which programs the event type not static and call it from the
southbridge.c file.

Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
 2017-10-02 22:31:32 +00:00
Marshall Dawson
eecb794c96 amd/stoneyridge: Move pm/smi_read/write functions to util file 
Pull all pm_read and write, smi_read and write variants into a single
file.

Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
 2017-10-02 22:27:38 +00:00
Marshall Dawson
16745e39b6 amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge 
Duplicate existing pm_read and pm_write and create 32-bit register
access functions.

Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21749
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
 2017-10-02 22:27:19 +00:00
Marshall Dawson
f7ace0da45 amd/stoneyridge: Fix pm_read16 argument size 
Make pm_read16() consistent with the other PM register access functions.

Change-Id: Iba017b8090ed07d8684cc7f396a3e9a942b3ad95
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
 2017-10-02 22:27:00 +00:00
Richard Spiegel
38f19400f9 soc/amd/stoneyridge/southbridge.c: Remove preprocessor #if 
Replace #if and #endif with runtime <if (condition) {> and <}>

Code Files: southbridge.c
BUG=b:62200891

Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2017-10-02 16:08:17 +00:00
Marshall Dawson
e9b862eb2c amd/stoneyridge: Use generic SMM command port values 
Remove the old Hudson-specific SMM command port definitions and use the
ones in cpu/x86/smm.h.

Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-09-30 20:34:28 +00:00
Marc Jones
dfeb1c4da9 stoneyridge: Rename hudson to southbridge 
Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.

BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.

Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-14 14:50:51 +00:00