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3dff32c8041bb6d1ee4b2c5a8681ec0259b46bf6
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12 Commits

Author SHA1 Message Date
Elyes HAOUAS
3dff32c804 nb/i945: Improve code formatting 
Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-11 09:19:13 +00:00
Angel Pons
4b42983c7a src/northbridge: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Id2cb642baa764fd69543460ba869cd822ab5acad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-04-05 17:44:14 +00:00
Elyes HAOUAS
0c9630eeff nb/intel/{i945,sandybridge}/bootblock.c: Fix typo 
Change-Id: I3def16c7bbf9d1997930832185beb8228ae163bd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38245
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-01-10 15:25:12 +00:00
Kyösti Mälkki
de64078102 bootblock: Provide some common prototypes 
The split of bootblock initialisation to cpu, northbridge and
southbridge is not specific to intel at all, create new header
<arch/bootblock.h> as AMD will want some of these too.

Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-12-14 14:08:57 +00:00
Arthur Heymans
e27c013f39 nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK 
Console init in bootblock will be done in a separate CL.

Change-Id: Ia2405013f262d904aa82be323e928223dbb4296c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36795
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-15 16:45:48 +00:00
Kyösti Mälkki
065857ee7f arch/io.h: Drop unnecessary include 
Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-03-04 15:08:03 +00:00
Kyösti Mälkki
f1b58b7835 device/pci: Fix PCI accessor headers 
PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.

Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-03-01 20:32:15 +00:00
Martin Roth
5474eb15ef src/northbridge: Add and update license headers 
This change adds and updates headers in all of the northbridge files
that had missing or unrecognized headers.  After this goes in, we can
turn on lint checking for headers in all northbridge directories.

Change-Id: I8cd7c04ddb8e58946dcdf9c7c125e23698647a73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2018-05-29 22:36:37 +00:00
Elyes HAOUAS
96184e9f2d nb/intel/i945/bootblock.c: Correct comment 
Change-Id: Ic28ff80eb1dae6d0a307e2a1b73e8129fffbac13
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2018-05-11 09:05:40 +00:00
Arthur Heymans
70a8e34853 nb/intel/i945: Fix errors found by checkpatch.pl 
Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18704
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
 2017-03-22 17:55:37 +01:00
Kyösti Mälkki
6f66f414a0 PCI ops: MMCONF_SUPPORT_DEFAULT is required 
Doing PCI config operations via MMIO window by default is a
requirement, if supported by the platform. This means chipset
or CPU code must enable MMCONF operations early in bootblock
already, or before platform-specific romstage entry.

Platforms are allowed to have NO_MMCONF_SUPPORT only in the
case it is actually not implemented in the silicon.

Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17693
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2016-12-07 12:59:28 +01:00
Kyösti Mälkki
032c23db08 intel/i945: Use MMCONF_SUPPORT_DEFAULT 
Change all PCI configuration accesses to MMIO on all boards
with i945 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.

Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3584
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Nico Huber <nico.huber@secunet.com>
 2013-07-04 00:53:39 +02:00