3dff32c804
Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
24 lines
888 B
C
24 lines
888 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <arch/bootblock.h>
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#include <device/pci_ops.h>
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#include "i945.h"
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void bootblock_early_northbridge_init(void)
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{
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uint32_t reg;
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/*
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* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
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* because CONFIG_MMCONF_SUPPORT is set to true. That way all subsequent non-explicit
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* config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final assumption is that
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* no assembly code is using the CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
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*/
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reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
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pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
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}
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