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4087 Commits

Author SHA1 Message Date
Elyes Haouas
a361d35b8d nb/intel/pineview: Use read32p() 
Change-Id: Ie2b1131d7db4b81bd6eb2df7a5ba8a6e8b54539b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-12-06 19:46:17 +00:00
Elyes Haouas
9a83eae71e nb/intel/haswell: Use {read,write}32p() 
Change-Id: Ibbefa3d57b17a6a8eb0831eeadf6d629e2765567
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-12-06 19:45:59 +00:00
Elyes Haouas
a2389ef316 nb/intel/x4x: Use read32p() 
Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-12-06 19:45:05 +00:00
Elyes Haouas
421f1ee294 nb/intel/e7505: Use read32p() 
Change-Id: I78337cf822cfae177b9ef3040641057a84e90e15
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-12-06 19:44:41 +00:00
Elyes Haouas
4b7d4054d9 nb/intel/sandybridge: Use read{8,32}p() 
Change-Id: I3bbb2f02a2dc182956deffc554a6b161a93ad963
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-12-06 19:44:26 +00:00
Elyes Haouas
ee4646e70e nb/intel/sandybridge: Use write32p() 
Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-06 15:06:27 +00:00
Arthur Heymans
98c92570d9 cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm 
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.

This removes the need for a magic lapic in the devicetree.

Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-05 14:22:12 +00:00
Elyes Haouas
a521d66116 nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clock 
Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-12-02 14:44:41 +00:00
Elyes Haouas
5a845ee894 nb/intel/pineview: Remove unused 'gpu_lvds_use_spread_spectrum_clock' 
'gpu_lvds_use_spread_spectrum_clock'is only used on i945.

Change-Id: I0f63f18d3f57ef8774f22ca9eb8c20dd39c56cdc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70147
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-02 14:40:22 +00:00
Arthur Heymans
1eecb8c814 nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree 
Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-01 10:28:10 +00:00
Arthur Heymans
22d6ee8d9c nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree 
Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-01 10:28:03 +00:00
Arthur Heymans
2fb6f68ef0 nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree 
Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-01 10:27:52 +00:00
Arthur Heymans
cdb26fd011 cpu/intel/model_206ax: Remove fake lapic device 
Instead of using a fake lapic device hook up the cpu cluster to chip
cpu/intel/model_206ax.

The lapic device is also not needed as the mp init will allocate it for
the BSP at runtime.

Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2022-12-01 10:27:31 +00:00
Arthur Heymans
d52bfbb6aa cpu/intel/sandybridge: Use enum for ACPI C states 
Also remove the now unnecessary comments from the devicetree.

Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2022-12-01 10:27:10 +00:00
Arthur Heymans
fade723b25 nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree 
Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69291
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-11-30 15:58:19 +00:00
Arthur Heymans
691d58f999 nb/intel/sandybridge: Add a chipset devicetree 
This only moves CPU configuration to a common place. Other PCI devices
can be done in follow-ups.

Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-11-30 15:19:06 +00:00
Kyösti Mälkki
f2b9852a8e nb/intel/e7505: Hook up PCI domain and CPU ops to devicetree 
Change-Id: I70fb470b63ddd06f1d1e34deaea296d81e24f75f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70058
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-11-30 04:05:55 +00:00
Kyösti Mälkki
560c3f5ccf aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG 
Both SMM_ASEG and SMM_TSEG choices work.

There is periodic TCO timeout occurring.
At least with DEBUG_SMI kernel reports low memory corruption.

Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2022-11-28 10:05:28 +00:00
Arthur Heymans
dd96ab6987 cpu/intel/haswell: Move chip_ops to cpu cluster 
The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.

Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2022-11-25 15:03:39 +00:00
Elyes Haouas
3a9980767e src/northbridge: Remove unnecessary space after casts 
Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-11-22 13:46:09 +00:00
Elyes Haouas
799c321914 cbmem_top_chipset: Change the return value to uintptr_t 
Get rid of a lot of casts.

Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
 2022-11-18 16:00:45 +00:00
Kyösti Mälkki
ac435b4b91 intel/haswell,lynxpoint: Fix out() parameter order 
Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2022-11-17 13:34:24 +00:00
Kyösti Mälkki
8d14633dfb nb/intel/ironlake,sandybridge/gma: Fix out() parameter order 
Change-Id: I4baa2e06d336736caf5505a05ed4353bcbfdb517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-11-17 13:33:33 +00:00
Elyes Haouas
185b16d946 nb/amd/pi/Kconfig: Drop unused Kconfig symbol 
Change-Id: I713b3fed3fc6d55139badec93a67943dd93ced2a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69333
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-11-17 13:25:21 +00:00
Kyösti Mälkki
8e679f72e9 sb/intel/i82801dx: Improve LPC device early init 
Make the implementation more similar to i82801gx, enabling
ACPI PM and GPIO register spaces already in bootblock.

Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2022-11-17 07:46:58 +00:00
Arthur Heymans
62eb94c9d3 nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetree 
Change-Id: I9dd254eddc12966154776d8a2d43f002567e758f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69290
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-11-14 22:34:23 +00:00
Arthur Heymans
b291dc8776 nb/intel/ironlake: Work around unused variable warning 
It's not clear whether this variable should actually be used or not so
leave it be with a FIXME comment.

Change-Id: I4892600bfec55830acae56d2b293947c2d9ddd07
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69237
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-11-12 14:45:32 +00:00
Kyösti Mälkki
7b73e85283 Revert "mb/aopen/dxplplusu: Remove board" 
This reverts commit eb76a455cd
and applies minor fixes to make it build again.

PARALLEL_MP was working prior to board removal and no
relevant SMI handlers were implemented. So NO_SMM choice
is now selected.

Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2022-11-09 18:10:54 +00:00
Arthur Heymans
600fa266bd nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree 
Change-Id: I955274bc6bda587201f130762c0735c36f5501d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-11-09 14:30:12 +00:00
Arthur Heymans
03a6ccd20d sb/amd: Remove dropped platforms 
This code is now unused by any platform.

Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-07 13:59:17 +00:00
Arthur Heymans
1a010236cf nb/amd/agesa: Remove leftover code 
This code is now unused by any platform.

Change-Id: I5464daa8cfb8231e2b19447c343fc80ab1d68ce8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69119
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-07 13:59:06 +00:00
Arthur Heymans
81a4fefce2 cpu/amd/agesa: Remove leftover code 
Now that all agesa CPUs are removed this code is unused.

Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-07 13:58:48 +00:00
Arthur Heymans
49af4f7f91 {cpu/nb}/amd/family16: Remove platform 
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I589f30ccf81b6cf243ac7cbf8320a3f830649ad8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69117
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-07 13:58:23 +00:00
Arthur Heymans
9a458e4e58 {cpu/nb}/amd/family15tn: Remove platform 
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I18eb1c1ccad16980a4e57318dec411b82c45b25a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69116
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-07 13:58:01 +00:00
Arthur Heymans
dbdf170dcd {cpu/nb}/amd/family14: Remove platform 
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: Ieaac0a32e71d208b66fd2c4e26f5349abc921d4f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69115
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-07 13:57:38 +00:00
Arthur Heymans
eb76a455cd mb/aopen/dxplplusu: Remove board 
This board use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-07 13:57:22 +00:00
Elyes Haouas
f2503fce3f nb/intel/pineview: Specify supported memory types 
Change-Id: If40010abdf180e40c2aab7a991c7382dc5b2d7d5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-04 00:57:00 +00:00
Elyes Haouas
649c8cb81c nb/intel/x4x: Specify supported memory types 
Change-Id: I07c24ece29616fa008da0935c3fe71e35f16ed2d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-04 00:56:44 +00:00
Elyes Haouas
9ee9cd30a2 nb/intel/sandybridge: Specify supported memory types 
Change-Id: Ie43e818d03f411733e1bba5b7a4721c9a54ff4a4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-04 00:56:13 +00:00
Elyes Haouas
49af63b8a1 nb/intel/gm45: Specify supported memory types 
Change-Id: I3a3a45a1a36ea6ad0b8fb2d3ee78add0b38460ac
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-04 00:55:12 +00:00
Elyes Haouas
e845753ce4 nb/intel/i945: Specify supported memory type 
Change-Id: I3cc2a9786dfb1f8fb1ec8e78bde7c46c07f8da48
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-11-04 00:54:52 +00:00
Angel Pons
6397687940 nb/intel/gm45: Make polling loops more explicit 
Replace `while (...);` with `do {} while (...);` so that it's easier to
distinguish polling loops from something else, like function calls. The
`{}` can be understood as "nothing", so that the construct is naturally
read as "do nothing while (...)".

Another reason to prefer this method is that Jenkins does not complain.

Change-Id: Ifbf3cf072f8b817b2fdeece4ef89bae0822bb6e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-11-03 02:01:14 +00:00
Elyes Haouas
901566597e nb/intel/i945/raminit: Use 'bool' for do_reset 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I692b86bba28853186185846f63dad1dcbfce1eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-10-22 05:14:35 +00:00
Elyes Haouas
d9dade3cb9 nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-10-22 05:14:11 +00:00
Elyes Haouas
26fc2a40ae nb/intel/i945/raminit: Use 'size_t' for banksize[] 
Change-Id: I4fb845bb4145d47aea39d7e5493d854d00e289aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-10-22 05:12:22 +00:00
Elyes Haouas
4c0299fbc8 nb/x4x/dq_dqs.c: Use 'enum cb_err' 
Change-Id: I94dd6b1bb81bbc38ac5f89469b3ed7c83ca2a498
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-10-21 14:35:26 +00:00
Elyes Haouas
6f9786bbcc nb/intel/x4x/raminit.c: Use 'enum cb_err' 
Change-Id: I22d7e724e69b41c9fabdef785276dc428be2b400
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-10-21 14:32:40 +00:00
Elyes Haouas
60bdb327c6 nb/intel/i945/rcven.c: Use read32p() 
Tested on unsupported mainboard (945g-m4).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1935308cc50abd651b52d6290d66180905c6a521
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68087
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2022-10-21 14:30:01 +00:00
Elyes Haouas
72c2e11beb nb/intel/i945/i945.h: Drop useless guard 
i945.h file is not used to generate asl files.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68215
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-10-20 19:39:53 +00:00
Elyes Haouas
1a847a11be nb/intel/i945: Clean up includes 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-10-20 17:29:48 +00:00