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33711 Commits

Author SHA1 Message Date
Kyösti Mälkki
564b4c5453 soc/amd,intel: Drop leftover GNVS includes 
Change-Id: Ia55d53a9a40846db335aabbe4df8e87f6172f712
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-30 17:19:03 +00:00
Felix Held
a21690ba12 soc/amd/stoneyridge/southbridge: replace southbridge prefix with fch 
This aligns the function names with Picasso and Cezanne. Also move the
fch_* functions in the header file in the order they get called.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49db8021edae5e537f043bf52eea1be54dc46eca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-01-30 17:17:48 +00:00
Felix Held
ffc87e9cbe soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls 
Cezanne doesn't have ACPI support yet, but in this case the function
always returns 0, so it can already be used.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1f5e1f31bf1e52988fcef90daf7b93169e21cbb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50126
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 17:17:24 +00:00
Felix Held
ac86cf33bf soc/amd/picasso/chip: add missing acpi/acpi.h include 
acpi_is_wakeup_s3() is defined in acpi/acpi.h

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53916cd15bb28484eb06be4d43f26152de159391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50125
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 17:17:01 +00:00
Subrata Banik
349b64f37a soc/intel/common/block: Create PCIE related macros 
Add generic PCIE RP related macros for SoC layer to use.

Change-Id: I84d02daded5cfe11120f099dc80c00ac0ec795f1
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-01-30 14:38:53 +00:00
Subrata Banik
0b53d8b883 soc/intel/alderlake: Remove pch.h from SoC directory 
Remove unnecessary include of soc/pch.h from
- bootblock/pch.c
- bootblock/report_platform.c
- bootblock/uart.c

Define PCIE_CLK_XXX macro inside chip.h for mb/devicetree.cb to
consume.

Change-Id: Ic08ef586d4590462434ba2c64e21dd802ccc6800
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50132
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 14:38:38 +00:00
Subrata Banik
1d18c8e3c8 mb/intel/adlrvp: Remove unnecessary whitespace 
Change-Id: I46af3e789de10ca6951b9e17f286c094c08a477f
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-01-30 14:38:24 +00:00
Felix Held
29148b9cd6 soc/amd/piasso/data_fabric: rename data_fabric_read_reg32 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib1b4da8f5daac2bae5e54f213accda03e121297d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-01-30 02:15:36 +00:00
Felix Held
db185182b5 soc/amd/picasso/data_fabric: factor out indirect address/index write 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id7bda8843a5ed0775424a056a05a6c4cb8269e49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-01-30 02:15:26 +00:00
Felix Held
230dbd6d3c soc/amd/cezanne: add empty ramstage FCH support 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-01-29 22:57:01 +00:00
Felix Held
faaafb4db1 soc/amd/picasso/fch: replace southbridge prefix with fch 
Also move the fch_* functions in the header file in the order they get
called.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b6c6ad744b26f8488015c38a84d7e21c7d7687a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50093
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-29 22:56:37 +00:00
Felix Held
86c24a2452 soc/amd/cezanne/chip: add FSP silicon init driver call 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id3dea23de0c7ce2fca4382e9fd4ec88aecaa55fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50092
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-29 22:56:17 +00:00
Kyösti Mälkki
ca71e135bc soc/intel: Remove duplicate call to acpi_wake_source() 
With SOC_INTEL_COMMON_BLOCK_ACPI=y the call was made twice,
possibly in the order:

  common/block/acpi.c: acpi_wake_source()
  common/acpi_wake_source.c: acpi_wake_source()

In this order later call would reset pm1i and gpei in GNVS.

Remove the implementation in block/acpi.c and rename existing
acpi_wake_source.c to block/acpi_wake_source.c.

Change-Id: I74fdae63111e3ea09000d888a918ebe70d711801
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-01-29 19:35:25 +00:00
Angel Pons
816a41c904 mb/emulation/qemu-q35: Consolidate host bridge definitions 
Move all Q35 register definitions into the q35.h header. Note that real
hardware does not have EXT_TSEG_MBYTES, because it is QEMU-specific.

Change-Id: I4c86ac0bb05563dee111b9b4a4a71c1c31198acd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50024
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-29 18:36:22 +00:00
Angel Pons
899525d92c mb/emulation/qemu-q35: Rename header 
The emulated northbridge is Q35. GM35 does not exist.

Tested, still boots.

Change-Id: Id8e114a43b54b71087d09d143176ed94329ab7af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-01-29 18:36:14 +00:00
Angel Pons
7d638784a2 device/Kconfig: Declare MMCONF symbols' type once 
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once.

Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-29 17:46:55 +00:00
Angel Pons
7830af3c8d mb/purism/librem_bdw: Turn comments into code 
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change.

Change-Id: Iec84fc2b43c23ea85f5cf13d9f0bace73e448c97
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-01-29 16:41:17 +00:00
Kyösti Mälkki
22ecdbe9f3 soc/intel: Drop CMEM from GNVS 
Already tagged as obsolete_cmem in <soc/nvs.h> files.

Change-Id: I8ba2a79f866fa07f1b4ae7291c72c91db5027911
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50043
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-29 16:25:25 +00:00
Kyösti Mälkki
6271dd8459 soc/intel/baytrail,broadwell: Use resume_from_stage_cache() 
Change-Id: Ie7b8bd02c3bb92c6ab9071941abbd90afef82601
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-29 10:54:13 +00:00
Kyösti Mälkki
e0165fbc94 stage_cache: Add resume_from_stage_cache() 
Factor out the condition when an attempt to load
stage from cache can be tried.

Change-Id: I936f07bed6fc82f46118d217f1fd233e2e041405
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-29 10:53:33 +00:00
Kyösti Mälkki
cdaddde067 mb/emulation/qemu-q35: Rename PICF to PICM in ASL 
Change-Id: I395056a164b6597b6fb3dfda0d85f9a0374cd893
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-01-29 10:21:54 +00:00
Kyösti Mälkki
62d6f1f943 ACPI: Do minor improvements on GNVS 
Reorder the support functions to make a bit more sense,
allocations happen first. Add related comments about the
bootstate these are to be called from.

Change-Id: Ie6d66f6e4c30519dee4520f6e9dec3c8c678ab57
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-29 10:21:25 +00:00
Kyösti Mälkki
0a54685b29 drivers/intel/fsp1_1: Drop s3_resume parameter to load_vbt() 
Change-Id: Iaba88026906132b96fe3db3f05950df0e7eef896
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-29 10:20:47 +00:00
Kyösti Mälkki
d0bc92df73 intel/fsp1_1: Declare fsp_load() as static 
The function has only one local call-site.

Change-Id: I623953796e6cd3a8e5b4f72293d953b61f14a5a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49999
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-29 10:15:24 +00:00
Frans Hendriks
ae38035d3a vc/google/chromeos/Kconfig: Remove unused NO_TPM_RESUME 
lint-008-kconfig reports unused symbol NO_TPM_RESUME.

Remove NO_TPM_RESUME.

BUG = N/A
TEST = Build Intel Elkhart Lake with Chrome EC enabled

Change-Id: I257ebcb4c42036d1476b9dc8e6d46fcc8c05f452
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-29 09:40:19 +00:00
Frans Hendriks
851571249f superio/nuvoton/common/Kconfig: Remove HWM config 
lint-008-kconfig reports unused symbol
SUPERIO_NUVOTON_COMMON_HWM.

Remove SUPERIO_NUVOTON_COMMON_HWM.

BUG = N/A
TEST = N/A

Change-Id: Ifad73f9ca4659e7b981a94c1e002e129d1b3388d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-29 09:39:43 +00:00
Felix Held
33c548b1ba soc/amd/picasso/Kconfig: order SOC_AMD_COMMON* selections alphabetically 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I66e7984e032a2b5fc6fa1ca6843a337424e5c02f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-29 00:40:17 +00:00
Elyes HAOUAS
cdad79659d mb/google/butterfly: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are same.

Change-Id: I85edf649a5170a1658fb135b797c1c6e1d2a9d70
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-28 21:37:14 +00:00
Elyes HAOUAS
94239cd6b1 mb/gizmosphere/gizmo2: Convert to ASL 2.0 syntax 
Generated build/dsdt.dsl files are same.

Change-Id: I0a4af7ebe6114338c2e8fb5fdf39a1de2cd47138
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-28 21:34:38 +00:00
Elyes HAOUAS
258f766e56 mb/gigabyte/ga-b75m-d3h: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' are identical.

Change-Id: Ic9b7dfd786ff8e1512c8678590a1dad7c984bca8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-28 21:34:02 +00:00
Elyes HAOUAS
c9c7e2d54f mb/hp/pavilion_m6_1035dx: Convert to ASL 2.0 syntax 
Generated 'Build/dsdt.dsl' are identical.

Change-Id: Id48df4fa0f8e5486636292ad11b8a86e71db4b17
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46080
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 21:33:40 +00:00
Elyes HAOUAS
3555b2f9f3 mb/asrock/e350m1: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' are identical.

Change-Id: Ief7ea77f8081cd6b7fb18fbf1d25c7394daca07d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46154
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 21:33:12 +00:00
Elyes HAOUAS
bebe4fbf40 mb/hp/abm: Convert to ASL 2.0 syntax 
Generated 'Build/dsdt.dsl' are identical.

Change-Id: Ie93dd1f6de1357cb3f448ed79a33b688abd91731
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-28 21:32:36 +00:00
Elyes HAOUAS
849a553505 mb/asrock/imb-a180: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' are identical.

Change-Id: I100b6c596d8a1dd74f096f71675026618da32e6f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-28 21:32:26 +00:00
Elyes HAOUAS
2cbe43890b mb/amd/thatcher: Convert to ASL 2.0 syntax 
Change-Id: If1869d091f9c78db7e308143d96b5d3046510ac8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46152
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 21:32:06 +00:00
Elyes HAOUAS
693511033a mb/amd/parmer: Convert to ASL 2.0 syntax 
Change-Id: I563cd549858429049223677ebc503f9c9304baa0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46149
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 21:31:49 +00:00
Elyes HAOUAS
85a2026800 mb/amd/padmelon: Convert to ASL 2.0 syntax 
Change-Id: I88c1c907916c3de51f6b3b72f7a49e90a1b1a383
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46148
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 21:31:34 +00:00
Felix Held
2976d3286e soc/amd/cezanne/Kconfig: move selections in alphabetical order 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99ac82b717e5efb6521040e88a3cfa5f09910be8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50010
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 20:47:59 +00:00
Chris Wang
ad4f6d7c6e soc/amd/picasso: allow USB_PD port setting override 
Allow to override the RFMUX setting if the board does not use PD chip.

BUG=b:177389383
BRANCH=none
TEST=Build; Check the USB_PD port been override.

Change-Id: Idd559b67668846805005a6e00f5a84655310f348
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49932
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 20:44:27 +00:00
Elyes HAOUAS
d4ed0e1c48 mb/biostar/a68n_5200: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are same.

Change-Id: I122f27bf7e7b809802efdbd443694b3d6e715108
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-28 18:03:02 +00:00
Elyes HAOUAS
c102bbd2ad mb/elmex/pcm205400: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are same.

Change-Id: I1cec4049adac74270641736709774156628b2539
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-28 18:02:34 +00:00
Daniel Gröber
8438927879 treewide: Remove unused #includes of spi_winbond.h 
We want to add some function declarations as static_testable to this
header but including it in a .c file outside of tests will yield a gcc
warning like:

    error: 'function' declared 'static' but never defined
      [-Werror=unused-function]

It seems these includes aren't necessary anyways so we just remove
them.

Change-Id: I17147136579140b94728ceb1c369b1348714bc53
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2021-01-28 14:19:14 +00:00
Arthur Heymans
93cb1809a2 cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZE 
This fixes a regression introduced by
Commit 985821c (cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE)
where the CAR base is not aligned to its size.

Change-Id: If54cb178e86426e1491dda4047302632d876a8f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50029
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 12:34:52 +00:00
Patrick Georgi
f9e24ddf86 mb/system76/oryp5: Fix up DSDT 
We started depending on dsdt_top.asl in dsdt.asl but this newly added
board wasn't adapted yet, so have it catch up.

Change-Id: If00280a33fd9e5c3ef1b3d07c41e81ed18013714
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50021
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 11:03:56 +00:00
Sridhar Siricilla
0df42f31b6 soc/intel: Remove selection of ME_REGION_ALLOW_CPU_READ_ACCESS 
The patch removes selection of ME_REGION_ALLOW_CPU_READ_ACCESS config in
the SOC_INTEL_CSE_LITE_SKU Kconfig definition since the
ME_REGION_ALLOW_CPU_READ_ACCESS Kconfig selection is done based on the
SOC_INTEL_CSE_LITE_SKU Kconfig in the
southbridge/intel/common/firmware/Kconfig.

TEST=Verified build for JSL

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I9969cce0d433657dd27bab71c132356fb28a35c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50012
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 09:31:47 +00:00
Sridhar Siricilla
315ebb2571 southbridge/intel: Define default value for ME_REGION_ALLOW_CPU_READ_ACCESS 
The patch defines default value for ME_REGION_ALLOW_CPU_READ_ACCESS config.
It sets value 'y' if CSE Lite SKU is integrated, otherwise value 'n'. The
config ME_REGION_ALLOW_CPU_READ_ACCESS ensures host has read access to ME
region when the LOCK_MANAGEMENT_ENGINE is enabled and CSE Lite SKU is
integrated.

TEST=Verified build for JSL

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I680a23e27ae2bf4d85bf919134c47882f308af56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49891
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-28 09:31:39 +00:00
Frans Hendriks
2659d40905 mb/emulation/qemu-q35: Solve lint-001 error 
lint-001-no-global-config-in-romstage error on
D0F0_PCIEXBAR_LO.

DOF0_PCIEXBAR_LO is defined in bootblock.c and
romstage.c.
Place D0F0_PCIEXBAR_XX in local gm35.h.

BUG = N/A
TEST = Build and boot QEMU x86 q35/ich9

Change-Id: Ia5ac9eb797de996186282193647313b9f7b42624
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
 2021-01-28 09:30:32 +00:00
Johnny Lin
ca083db4d3 xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices 
The values can be used during SMBIOS type 16 creation.

Tested=On OCP Delta Lake, dmidecode -t 16 to verify.
Handle 0x000A, DMI type 16, 23 bytes
Physical Memory Array
        Location: System Board Or Motherboard
        Use: System Memory
        Error Correction Type: Single-bit ECC
        Maximum Capacity: 1146 GB
        Error Information Handle: Not Provided
        Number Of Devices: 6

Change-Id: Id8f92dc96a7a3eb2e6db330adda98a7fe6d516c8
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-28 09:30:09 +00:00
FrankChu
d22f256e03 mb/google/dedede/var/galith: Add Wifi SAR for convertibles 
Add wifi sar for galith
Using convertible mode of fw config to decide to load custom wifi sar or not.

BUG=b:176206495
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Cq-Depend: chromium:2649378,chrome-internal:3559387
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I0f9a7ddedef550317da4bf798317619ffd1fa979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2021-01-28 09:27:11 +00:00
Subrata Banik
ac8c357ddc mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematics 
1. GPP_E5 =>  Remove unused GPIOs
2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO

Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-01-28 09:26:48 +00:00