Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bit 63 is part of GPIO_GPE_NW group 1 and group 2 starts from bit
64. This change corrects macro name to GPIO_GPE_NW_95_64 to reflect
this.
BUG=b:77224247
Change-Id: Ib94617ad102eea5084281f0dda3475e33d3a7833
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for APL and GLK.
Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since we do not know before hand the memory range initialized by FSP memory
init until it completes and as memory gets accessed from within FSP memory
init to migrate FSP from CAR to memory, we need to add this mapping in
coreboot.
Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.
Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With
PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table
entry for this range which caused a page fault. Since this test
is anyway not exhaustive, we will skip the memory test in FSP.
There is an option to do PCIe power sequence from within FSP if provided
with the GPIOs used for PERST to FSP. Since we do this from coreboot,
will skip the PCIe power sequence done by FSP.
FSP does not know what the clock requirements are for the device on
SPI bus, hence it should not modify what coreboot has set up. Hence
skipping SPI clock programming in FSP.
CQ-DEPEND=CL:*627827
BUG=b:78599939, b:78599576, b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26284
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds more parameters to bootblock_main_with_timestamp() to
give callers the opportunity to add additional timestamps that were
recorded in the platform-specific initialization phase.
Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for
any root hubs that may be present.
Recent Intel platforms route all ports to an XHCI controller
through a root hub. This is supported by considering the root
hub to be USB port type 0, the USB 2.0 ports to be type 2, and
the USB 3.0 ports to be type 3.
This was tested with a Kaby Lake platform by adding entries to
the devicetree and checking the resulting SSDT.
Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add APIs and required parameters for creating Realtek 5682 SSP
endpoint in NHLT table.
BUG=b:79235534
TEST=check that NHLT table defined is created properly.
With the series merged & required driver support in kernel.
Verify Headset Audio playback.
Change-Id: Ic26a0b881f77af64ba00fd714b08c0f17c0acb3d
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/26057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
ifdtool has relied on one of the fields within FCBA(read_freq) to
determine whether a platform supports IFD_VERSION_1 or
IFD_VERSION_2. However, newer platforms like GLK and CNL do not have
read_freq field in FCBA and so the value of these bits cannot be used
as an indicator to distinguish IFD versions. In the long run, we need
to re-write ifdtool to have a better mapping of SoC to IFD fields. But
until that is done, this change adds a list of platforms that we know
do not support read_freq field but still use IFD_VERSION_2. This
change also updates GLK and CNL to pass in platform parameter to
ifdtool.
BUG=b:79109029, b:69270831
Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With only one entry for Write Protect gpio in the OIPG package, the sysfs
entry /sys/devices/platform/chromeos_acpi/GPIO.x is created as "GPIO"
instead of "GPIO.x". This was causing crossytem to return error for wpsw_cur.
BUG=b:78009842
Change-Id: Ica60f342420d95d09a45580f2f940443c03601de
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support and enalbe cache-as-ram paging for glk to work around
a cache-as-ram corruption issue. glk executes verstage, romstage,
and FSP-M directly out of cache-as-ram (just like apl). However,
the front end on glk is very agressive about pulling cache lines
into L1I for potential execution. When the snoops hit in the L1D
and the cache lines are dirty the processor writes the line back.
However, there is no backing store for the dirty lines to go. As
such when the line is pulled back in the value is all 0xff's,
corrupting cache-as-ram.
To fix the issue one needs to enable paging with NX (no execute)
permissions which prevents the above actions from happening because
the TLB will indicate that shouldn't be fetched into the instruction
cache since data will be marked no execute.
The generated page tables are added to cbfs and only added to the
COREBOOT cbfs as they are only consumed in the early cache-as-ram
stages.
The page tables generated with:
$ go run util/x86/x86_page_tables.go \
--iomap_file=src/soc/intel/apollolake/glk_page_map.txt \
--metadata_base_address=0xfef00000 \
--pdpt_output_c_file=src/soc/intel/apollolake/pdpt.c \
--pt_output_c_file=src/soc/intel/apollolake/pt.c
Merged address space:
00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small
00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small
00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small
00000000fefc0000 -- 00000000ff000000 WB NX : 0 big 64 small
00000000ff000000 -- 0000000100000000 WP : 8 big 0 small
Total Pages of page tables: 5
Pages linked using base address of 0xfef00000.
BUG=b:72728953
Change-Id: Icde9cc0bf5079bb5821f4e59eb61e939c13d7062
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that an idt is available in every stage utilize it for exception
processing to help catch and debug issues.
BUG=b:72728953
Change-Id: I69e7f938f36f2e522b787e311fd148bb8fd41247
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25764
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's going to be necessary to know the i/o hole size as well
the amount of memory configured in the sytsem. Therefore, add
two helper functions:
memory_in_system_in_mib()
iohole_in_mib()
Both return values in units of MiB.
BUG=b:72728953
Change-Id: I481ba517c37f769e76d9e12b3631f5f99b5427a9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25738
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes our devicetree in sync with the FSP configuration.
Without this we see in boot logs "PCI: 00:00.2 not found,
disabling it". The reason being in FSP NPK device is disabled by
default. We can enable it by enabling the UPD parameter TraceHubEn.
If we enable it in FSP then the logs complain the NPK pcie device
is not seen.
BUG=b:76115112
TEST=Build for Octopus and check that the logs do not report
"PCI: 00:00.2 not found, disabling it".
Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On glk there's a 4MiB L2 cache all the time. Take advantage of that
by initializing a 1MiB cache-as-ram area.
BUG=b:72728953
Change-Id: Ia4e777a13607d8b70c05534b0a172f0ec6b04c51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25645
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On APL and GLK the i2c blocks use 133MHz input clock, but the
SPI blocks use a 100MHz input clock. Fix this so that the proper
target frequencies can be hit on the SPI controllers.
BUG=b:75306520
Change-Id: Iec36579894fa4633ac8d1035e6e7afec01af755f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.
BUG=b:75306520
Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MONITOR/MWAIT had an irremediable hardware bug for Apollolake.
This has been fixed for GLK. Therefore, make MONITOR/MWAIT based
C-states the default for GLK and disable IO-Redirection based
C-states used for Apollolake.
Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state
residencies with and without load.
Tested for S0ix entry and exit using:
"echo freeze > /sys/power/state" and "suspend_stress_test -c 500".
BUG=b:77639897
Change-Id: If648c25a9b26c04b278dce4af241d439790288ca
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/19718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get rid of custom opregion implementation and use drivers/intel/gma/opregion
implementation instead.
Test: boot Windows 10 on google/chell and google/edgar using Tianocore
payload with GOP init, observe Intel graphics driver loaded and functional.
Change-Id: I5f78e9030df12da5369d142dda5c59e576ebcef7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21703
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
Change-Id: I5aea15511c52d1191babf551feb237f4144683e4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PCIe de-emphasis is enabled by default. Thunderpeak Wi-Fi requires
it to be disabled. Therefore allow it to be configured via a
device tree setting.
TEST=On GLKRVP, verify Thunderpeak Wi-Fi card shows up in lspci when
de-emphasis is disabled in device tree.
Change-Id: Iae204768dfe00a638c764644c44c7cda269e73e0
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
glk has different memory profile values than apl. Therefore, a
translation is required to correctly set the proper profile value
depending on what SoC (and therefore FSP) is being used. Based on
SOC_INTEL_GLK Kconfig value use different profiles.
BUG=b:74932341
Change-Id: I6ea84d3339caf666aea5034ab8f0287bd1915e06
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25249
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpHotPlug in apollolake UPD is default enabled. This change adds a
config option to enable hotplug only if explicitly requested by
mainboard. This changes the default behavior on all apollolake boards
to have hotplug disabled.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add group information for each gpio community and use it to
calculate offset of a pad within its group. Original implementation
assumed that the number of gpios in each group is same but that lead to
a bug for cnl since numbers differ for each group.
BUG=b:69616750
TEST=Need to test again on SKL,CNL,APL,GLK
Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22571
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per FSP 2.0 specification and FSP SOC integration guide, its not expected
that SMBIOS Memory Information GUID will be same for all platform. Hence
fsp_find_smbios_memory_info() function inside common/driver code is not
generic one.
Removing this function and making use of fsp_find_extension_hob_by_guid()
to find SMBIOS Memory Info GUID from platform code as needed.
Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
