- 'git describe --match [0-9].[0-9]*' was giving me an error, so use
the basic 'git describe' command instead.
- If a .coreboot-version file exists, use that to determine the version.
This fixes the problem for coreboot releases.
- Don't run git for the versions unless it's being built from a valid
git repository. Use 0.0 as the default version for timeless or unknown.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5fae2f012cc9b9914d8803af8dd58a885358cb1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The `HyperThreading` FSP UPD is set according to the `hyper_threading`
CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option
as fallback in case options are disabled or otherwise unavailable. The
`HyperThreadingDisable` devicetree setting isn't used by any mainboard
but it overwrites the value of the FSP UPD. Remove it so that the CMOS
and Kconfig options work as intended.
Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ELOG_CROS_DIAG_RESULT_* codes should be consistent with the enum
definition of enumerated histograms.
Hence add comments based on the requirements of enum histograms in
histogram guidelines.
BUG=b:4047421
TEST=none
Change-Id: I1a1a7c863d5aa9496649f81dc94fd79a6ad482df
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70145
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DSI CMDQ offset of MT8186 is different from previous SoCs.
Therefore, we define two versions for DSI register header files. The v1
is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188.
BUG=b:244208960
TEST=build pass
BRANCH=corsola
Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70183
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For geralt project, we also support MIPI panel as our firmware display.
So add this patch to configure ddp to choose eDP display or MIPI panel
display.
BUG=b:244208960
TEST=test firmware display pass for both eDP and MIPI panel on MT8188
EVB.
Change-Id: I06f38b1889811274588c26e9284da4d502acf38b
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70181
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.
This removes the need for a magic lapic in the devicetree.
Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch adds PCIe based SD controller at RP 7 (from RP 11) with
Proto 1 schematics dated 11/30.
Additionally, added the RTD3 entries for the SD controller.
Finally, ensured that EN_PP3300_SD (GPP_D03) is configured in
bootblock and SD_PERST_L (GPP_D02) is configured in romstage to
meet the power cycle requirement.
BUG=b:242917011
TEST=Able to build and boot Google/Rex. SD card detection is due
for the Proto 1 hardware.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23d53e4d61ec36d2145f9e5816d97d13eb5b219e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70064
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This patch drops the usage of reading `board_id()` while performing
the GPIO configuration.
The reason to drop the board_id check is to ensure that GPIO
configuration for MLB (mainboard) would remain the same and the only
GPIO PIN configuration that differs would be due to usage of having
different DBs (daughter board) which will be taken care using
CBI (and fw_config.c file) in coreboot.
Additionally, drop unused early GPIO default configuration table.
BUG=b:260804656
TEST=Able to perform the GPIO configuration and able to boot
Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I96cafd1c904001cbf4199977e9e721afe5eab470
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Enable this feature, and it can use the probe statement in devicetree
to cache of fw_config field as oem string.
TEST=With CBI FW_CONFIG field set to 0x1561
localhost ~ # dmidecode -t 11
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
String 1: AUDIO-MAX98357_ALC5682I_I2S
String 2: CELLULAR-CELLULAR_PCIE
String 3: UFC-UFC_MIPI
String 4: WFC-WFC_MIPI
String 5: DB_SD-SD_GL9755S
Change-Id: I6cb35eb9c0fbe32764ca76bb7a929cc92fc38404
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70228
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NVMe is determined by a logical bit 1, not the physical SKU pin.
Thus, (logical) sku_id & 0x2 == 0x2 would mean that the device has
NVMe enabled on it. Previously, I thought that it was tied to a
physical pin, but this is not correct.
BUG=b:254281839
BRANCH=None
TEST=flash and boot on villager and make sure that NVMe is not
initialized in coreboot.
Change-Id: Iaa75d2418d6a2351d874842e8678bd6ad3c92526
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70230
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The devices in the list that was introduced in commit c66ea98577
("soc/intel/alderlake: provide a list of D-states to enter
LPM") are all internal. This CL skips the external buses (which caused
the addition of packages to non-existant paths such as
"_SB.PCI0.RP1.MCHC", and warnings from the kernel)
BUG=b:231582182
TEST=Built and tested on anahera by verifying SSDT contents
Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required
for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using
8254 timer counter 2 output. However when 8254 timer is used, S0ix
will not work as 8254 has to be gated instead. For further info on
s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified
Checklist).
This CL also disables s0ix because it is not required by the
platform.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67553
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Galago Pro 6 (galp6) is an Alder Lake-P board.
Tested with a custom edk2 UefiPayloadPkg.
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- M.2 NVMe SSD (with MZVL2500HCJQ)
- All USB ports
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Windows 10 and Linux 6.1
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- S0ix suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.0.6
- Internal flashing with flashrom v1.2-1087-gde016a17
Not working:
- Detection of devices in TBT slot on boot
Change-Id: I8940fb3777d7f18393ef50baec32f9445b375648
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA
common code to skip sending CSE EOP cmd during finalize operation
rather uses boot state machine (either payload load or payload boot)
to delay in sending EOP cmd to CSE.
BUG=b:260041679
TEST=Able to boot to Google/Rex with this patch and observed ~150ms
savings in boot time
Without this patch:
942:before sending EOP to ME 1,795,702 (354)
943:after sending EOP to ME 1,950,526 (154,824)
With this patch:
942:before sending EOP to ME 2,051,406 (35,484)
943:after sending EOP to ME 2,057,583 (6,177)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch allows to send late EOP cmd to CSE (after CSE .final)
using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD)
if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config.
Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()`
to make the function name more meaningful with its operation.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
