7567890110
soc/intel/common: Fix XHCI elog driver
...
Commit 56fcfb5twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-12-22 22:37:56 +00:00
7a66ffb34a
soc/intel/common/block/acpi: Fix get_cores_per_package
...
Current implementation uses CPUID 0Bh function that returns the number
of logical cores of requested level. The problem with this approach is
that this value doesn't change when HyperThreading is disabled (it's in
the Intel docs), so it breaks generate_cpu_entries() because `numcpus`
ends up being zero due to integer division truncation.
- Use MSR 0x35 instead, which returns the correct number of logical
processors with and without HT.
- Use cpu_read_topology() to gather the required information
Tested on Prodrive Hermes, the ACPI code is now generated even with
HyperThreading disabled.
Change-Id: Id9b985a07cd3f99a823622f766c80ff240ac1188
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-12-22 22:22:21 +00:00
8d127846bc
soc/intel/cannonlake: Add Iccmax and loadlines for CML-S
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Following up 3ccae2b7#606599 and pdg #610244 .
Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38288
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-22 22:21:00 +00:00
8ba96b91dc
soc/intel/apl/graphics: add missing left-shift
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According to doc# IHD-OS-BXT-Vol 2b-05.17 the cycle delay is in the bit
range 8:4 of register PP_CONTROL. The current code writes the value to
bits 4:0, though. Correct that by shifting the value left by 4 bits.
Change-Id: If407932c847da39b19e307368c9e52ba1c93bccd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-12-22 20:34:27 +00:00
e653942453
sb/intel/ibexpeak: Drop ChromeOS setup for GNVS
...
The CHROMEOS option was never used with ibexpeak, code was copy-pasted
and forked from bd82x6x. Since a custom ibexpeak/nvs.h was already made,
an accompanying globalnvs.asl is added here too without chromeos_acpi_t.
Change-Id: I16406516b51c13d49593bc8a3e1e5b868eea6f24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48766
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-22 17:29:13 +00:00
b3a411cc7d
sb,soc/intel: Drop unnecessary headers
...
Files under sb/ or soc/ should not have includes that tie those
directly to external components like ChromeEC os ChromeOS
vendorcode.
Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-22 17:28:23 +00:00
42af26c527
soc/amd/common/psp: Remove files from bootblock
...
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Change-Id: I8d775d2d813cf92245f3be4d41b3295ca6da18ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48798
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-22 17:07:07 +00:00
af55b3f927
soc/amd/stoneyridge: Remove unused psp.h
...
psp.h was first included when Stoney Ridge began loading the first
SMU firmware. That step was later moved from bootblock to romstage.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Change-Id: Id646390ce377143d09455f797de1b149dbb615b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48797
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-22 17:06:12 +00:00
cff6ad8c51
mb/google/volteer: Add GPIO to drobit support
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Add support for gpio driver for drobit
BUG=b:175351914
BRANCH=none
TEST=emerge-volteer coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com >
Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-12-22 16:08:59 +00:00
8d3c397285
mb/google/volteer: Update SPD table for drobit
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drobit memory table as follow:
value Vendor Part number
0x00 MICRON MT53E512M32D2NP-046 WT:E
0x00 HYNIX H9HCNNNBKMMLXR-NEE
0x01 MICRON MT53E1G32D2NP-046 WT:A
0x02 HYNIX H9HCNNNCPMMLXR-NEE
BUG=b:175351914
BRANCH=none
TEST=emerge-volteer coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com >
Change-Id: Icd9439f8449856d4ec6798a4e4310dd139bce05f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48496
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-22 16:08:51 +00:00
afd5fd6d76
mb/google/volteer: Update drobit device tree
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Update drobit device tree override to match schematics.
BUG=b:175351914
BRANCH=none
TEST=emerge-volteer coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com >
Change-Id: I48a3024df4270b111b90c4fb56847aad6e65bfa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Zhuohao Lee <zhuohao@google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-12-22 16:08:45 +00:00
490120e1bb
mb/clevo/cml-u: move gpio early init to bootblock_mainboard_early_init
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Move gpio early init to bootblock_mainboard_early_init to make the
bootblock console work as early as possible.
Change-Id: I619f7d0e15adae284b606dd20c3c1f04f3eafd7b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48801
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-22 13:44:16 +00:00
b2a749d4ac
Revert "mb/clevo/cml-u: drop duplicated configuration of UART pads"
...
This reverts commit 1a0071c711felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-12-22 13:43:17 +00:00
6c0aba2059
mb/google/zork/var/vilboz: Add enable acp_i2s_use_external_48mhz_osc flag
...
Add enable acp_i2s_use_external_48mhz_osc flag and then
WWAN sku will use external clock source at next build.
BUG=b:174121847
BRANCH=zork
TEST=build vilboz and check MISC_CLK_CNTL1.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com >
Change-Id: Ida747938373f648524b1e7f34bc69e372a69c4f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48556
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-22 03:47:15 +00:00
e05298b1d2
soc/mediatek/mt8192: Do dramc software impedance calibration
...
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com >
Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2020-12-22 03:00:56 +00:00
cc064c6c93
soc/mediatek/mt8192: Do EMI init before dram calibration
...
Reference datasheet:
External Memory Interface (EMI).pdf, Document No: RH-A-2020-0055.
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com >
Change-Id: I3b778698a09c999252fef3153ac1e869ea9d90cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
2020-12-22 03:00:32 +00:00
131f3435fc
soc/mediatek/mt8192: Do memory pll init before calibration
...
Memory PLL is used to provide the basic clock for dram controller
and DDRPHY. PLL must be initialized as predefined way.
First, enable PLL POWER and ISO, wait at least 30us, release ISO, then
configure PLL frequency and enable PLL master switch.
At last, enable control ability for SPM to switch between active and
idle when system is switched between normal and low power mode.
TEST=Confirm Memory PLL frequency is right by frequency meter
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com >
Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
2020-12-22 03:00:07 +00:00
63e2a84d59
soc/intel/xeon_sp: Use common block ACPI
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Use the common block ACPI to further reduce the duplicate code.
Change-Id: If28d75cbb2a88363d70e3ae6a2cace46cb6bbbab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48248
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-22 02:59:18 +00:00
f65945fe8c
Revert "mb/clevo/kbl-u: drop duplicated configuration of UART pads"
...
This reverts commit ccceb2250efelixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-12-21 22:12:41 +00:00
db27d6f6d0
mb/prodrive/hermes: Update USB 2.0 settings
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Test results show that USB signals look better with these settings.
Yes, there's a macro in the devicetree now. All ports use the same
settings except for the overcurrent pin, so this avoids redundancy.
Change-Id: Ib0dafab88d8dcc05388b724f6a7183c13ac64934
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48694
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-21 19:30:05 +00:00
3b879f46b4
mb/google/octopus/var/phaser: Add support for G2TOUCH Touchscreen
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Add devicetree configuration for G2TOUCH Touchscreen controller.
BUG=b:175513059
BRANCH=octopus
TEST=build bios, check i2c bus and verify touch screen works fine
Change-Id: Ib57597c4998f205c664e13befb4c44532b7dbd4f
Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2020-12-21 02:38:39 +00:00
2bea58db60
drivers/tpm/ppi_stub: Fix interface version
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The latest version defined by TCG is 1.3.
Change-Id: Idb12e2212d6d38c720c8fe989678724c871af6ef
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45569
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-21 02:38:28 +00:00
39d6927609
drivers/tpm: Implement full PPI
...
Implement the ACPI PPI interface as described in
"TCG PC Client Physical Presence Interface Specification" Version 1.3.
Add a new Kconfig that allows to use the full PPI instead of the stub
version compiled in.
This doesn't add code to execute the PPI request, as that's up to the
payload with graphical UI support.
Tested on GNU/Linux 5.6 using the sysfs interface at:
/sys/class/tpm/tpm0/ppi/
Change-Id: Ifffe1d9b715e2c37568e1b009e86c298025c89ac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45568
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-21 02:38:20 +00:00
f20151dfaa
mb/google/dedede/var/storo: Generate SPD ID for supported memory parts
...
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
H9HCNNNCPMMLXR-NEE
BUG=None
TEST=Build the storo board.
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com >
Change-Id: Ifd935865927bb9fccf95eb4924ca6986d0c19442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2020-12-21 02:37:39 +00:00
8dad8248d4
mb/google/dedede: Update Boten setting for USI PEN detection.
...
Update devicetree and gpio driving of boten that enable stylus
PEN detect signal is not dual-routed on Boten. Since the gpio_keys kernel
driver expects the pad to be owned by GPIO controller (i.e. configured for
GPIO IRQ), it cannot be configured for ACPI (i.e. SCI).
Thus, this change updates the GPIO configuration for GPP_C12 to
PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to
use WAKEUP_ROUTE_GPIO_IRQ. Additionally, the signal is marked as active
low in the device tree entry to indicate to the kernel driver that the signal
is inverted.
Not dual routing the signal results in wake source not being added to
eventlog when pen removal results in wake from S0ix.
BUG=b:160752604
BRANCH=dedede
TEST=Build and check behavior is expected.
Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com >
Change-Id: I74a17088da64c22ef1c74d201c80274fc65a44c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2020-12-21 02:37:29 +00:00
45a6ae35ef
soc/intel/xeon_sp/skx: Properly set up MTRR's
...
Don't depend on the MTRR setup left over from FSP-M ExitTempRam.
Change-Id: I299123b3cd3c37b4345102c20fda77bf261892a2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com >
2020-12-21 02:37:13 +00:00
08d8dd3bd3
soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES
...
Change-Id: I42ddea2c04bf1ecb2466db3d56d15d51bda486c8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com >
2020-12-21 02:37:04 +00:00
9c581a74f6
mb/prodrive/hermes: Enable S3/S4 resume
...
Change-Id: I75f83bcc6c65a048e87f7295a66526eb384afc5d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-12-21 02:36:47 +00:00
ce07b5c0ab
mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board
...
This patch adds initial support for Alderlake Intel Pre-CEP
board called shadowmountain.
BUG=b:175808146
TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max
Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829
Signed-off-by: V Sowmya <v.sowmya@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-12-21 02:36:40 +00:00
04da829a0f
volteer/variants/eldrid: Enable RTD3 for the NVMe device
...
Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.
BUG=b:161270810
TEST=tested on eldrid
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com >
Change-Id: I941c8a9bb3221ad90528c323cd0f267dc77d2af3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-12-21 02:36:31 +00:00
847043c207
soc/intel/common/block/acpi: Add soc MADT IOAPIC hook
...
Add a hook for SOCs to provide an IOAPIC MADT table. If the
SOC doesn't provide a table then a standard setting is used.
Change-Id: Ic818a634e4912d88ef93971deb4da5ab708c9020
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-12-21 02:35:21 +00:00
cbe1244071
soc/amd/picasso: Add UPDs for support eDP phy tunning adjust
...
Add UPDs for eDP phy tunning adjust
BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com >
Change-Id: I6df063f828447841ac9a6dba00a4aad2001f04df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
2020-12-21 02:34:32 +00:00
bf29a0d21f
amdfwtool: Add support of cezanne and renoir
...
Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-21 02:34:15 +00:00
a81703c37b
soc/intel/common/block/acpi: Make calculate_power() global
...
Change static calculate_power() function to global and update the name
to common_calculate_power_ratio() for SOC ACPI code use.
Change-Id: I0e2d118ad52b36859bfc6029b7dee946193841f4
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
2020-12-21 02:32:44 +00:00
1aa8fc3cef
drivers/intel/fsp2_0: recreate FSP targets on config change
...
When a different FSP binary was chosen in menuconfig, the split fd files
do not get updated. Thus, make them depend on `.config` to trigger a
rebuild when the config changes.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Change-Id: I54739eae50fa1a47bf8f3fe2e79334bc7f7ac3d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-12-21 02:32:16 +00:00
c5603145d3
Revert "mb/google/dedede: Update Imon slope and Offset Value for Drawcia"
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Falling back to default values for Imon slope and offset for Drawcia
This is as per recommendation from ODM based on calibration
This reverts commit 2ac88f2347maulik.v.vaghela@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48737
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com >
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.corp-partner.google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-21 02:32:05 +00:00
bc89e8337c
mb/google/dedede: Add GPIO to galtic support
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Add support for gpio driver for galtic
BUG=b:170913840
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com >
Change-Id: I01bb95545705efab1a2adf1582b6293fd89e6420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48684
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-21 02:31:50 +00:00
85adcdbff4
mb/google/dedede/var/madoo: Configure Acoustic noise mitigation UPDs
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Enable Acoustic noise mitigation for madoo and set slew rate to 1/8
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.
BUG=b:173765599
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com >
Change-Id: I968d8d43016e3569835b0a777335fa1d5c135f87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2020-12-21 02:31:42 +00:00
8cb922346f
mb/google/dedede: Update SPD table for galtic
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galtic memory table as follow:
value Vendor Part number
0x00 MICRON MT53E512M32D2NP-046 WT:E
0x00 HYNIX H9HCNNNBKMMLXR-NEE
0x01 MICRON MT53E1G32D2NP-046 WT:A
0x02 HYNIX H9HCNNNCPMMLXR-NEE
BUG=b:170913840
BRANCH=none
TEST=emerge-dedede coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com >
Change-Id: I30b8fe3f14e1af7bb5760530477f9311c6a4ee62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2020-12-21 02:31:34 +00:00
d800d5e3ac
zork: update gumboz variant
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gumboz is the dalboz/dirinboz follower.
update gumboz variant to align dirinboz settings.
BUG=b:174277853,b:173662179
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com >
Change-Id: I80c03d531761c02b68bd127d889c3ace2dd9e99e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
Reviewed-by: Kangheui Won <khwon@chromium.org >
2020-12-21 02:24:16 +00:00
ccceb2250e
mb/clevo/kbl-u: drop duplicated configuration of UART pads
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UART pads already get configured in bootblock by the UART driver in soc
code. Thus, drop the duplicated code from the mainboard.
Change-Id: I95565a74e19d693a7d5ead81e72592cc4ca2038c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2020-12-20 00:02:09 +00:00
1a0071c711
mb/clevo/cml-u: drop duplicated configuration of UART pads
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UART pads already get configured in bootblock by the UART driver in soc
code. Thus, drop the duplicated code from the mainboard.
Tested successfully on Clevo L141CU.
Change-Id: I05a459b0af79c75c31b1bb26ea1a1a40857ef9bf
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2020-12-20 00:02:02 +00:00
3b648baf03
soc/amd/picasso: move sb_clk_output_48Mhz from acp to fch
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Move sb_clk_output_48Mhz out of acp. It should be called unconditionally.
We may have another device need this clock e.g. superio chip.
BUG=b:174121847
BRANCH=zork
TEST= build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com >
Change-Id: I30ad6c60066f17cc83e7feb40675610f4853a022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2020-12-19 16:29:44 +00:00
dd32e653cf
soc/amd/picasso: Add acp_i2s_use_external_48mhz_osc flag
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If we have use external clock source for I2S, we don't need to enable
internal one. Add acp_i2s_use_external_48mhz_osc flag for the project
which uses external clock source.
BUG=b:174121847
BRANCH=zork
TEST= build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com >
Change-Id: Ica68ee2da5a05231eb6db0218bd0f19907507273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2020-12-18 19:55:12 +00:00
07462ef3d6
soc/amd/cezanne: add GPIO support
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This still uses the common GPIO code that supports setting up SMI/SCI
support for the GPIOs in all stages, which will get removed in future
patches, so for now the SoC's gpio.c needs to be included in all stages.
Change-Id: I6c12d1d6c605b7eb063eef62a1f71860f602f8dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48565
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-18 17:20:56 +00:00
02a5dddb01
soc/amd/cezanne: Add SMI support
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Change-Id: I83b9a91cbab297d032292997a4d5768b89fe97dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48645
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-18 17:20:41 +00:00
fad0a5b01c
vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1512_11
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List of changes:
FSP-S Header:
- Adjust UPD Offset for Reservedxx
- Rename UPD Offset UnusedUpdSpace44 -> UnusedUpdSpace45
Change-Id: If0c18cbb556fc41786391464b76d7c9cc19eab0d
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-12-18 16:21:29 +00:00
8edb48baa6
util: Modify LPDDR4 spd_tools to generate SPDs for ADL boards
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Generates de-duplicated SPD files using a global memory part
list provided by the mainboard in JSON format.
BUG=b:173132516
Change-Id: I4964ec28d74ab36c6b6f2e9dce6c923d1df95c84
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48526
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-12-17 21:56:43 +00:00
2e0053b840
azalia: Use azalia_enter_reset function
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Also tidy up some adjacent comments.
Change-Id: I2e881900a52e42ab3f43ffe96cfbdcc63ff02e23
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-12-17 20:25:09 +00:00
a1a317ebf6
soc/intel/common/hda_verb.c: Clarify mask usage
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The `azalia_set_bits` will mask out all bits, so just use zero for
clarity. The resulting behavior is the same in both cases.
Change-Id: I27777f1e836fa973859629d48964060bec02c87a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-12-17 20:17:44 +00:00
