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Author SHA1 Message Date
Elyes HAOUAS
8684643911 soc/amd/stoneyridge/acpi: Convert to ASL 2.0 syntax 
Generated dsdt.dsl files are same.

Change-Id: Ife9bb37817815beec6dad4bc791abba4d91abe00
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2021-02-01 08:47:17 +00:00
Angel Pons
11fdb17564 soc/intel/broadwell/pch/sata.c: Don't enable Bus Master 
Bus Master is not required and reference code does not set it.

Change-Id: I2f70486f96cf3dcaba74283293b93b9747cd0300
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2021-02-01 08:47:06 +00:00
Patrick Rudolph
3fa23b8c00 soc/intel/*: Get rid of custom microcode caching 
Get rid of custom microcode caching in MPinit and SGX code and
use the caching introduced in intel_microcode_find() instead.

Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-01 08:46:30 +00:00
Frans Hendriks
7aaea37e37 device/oprom/include/x86emu/fpu_regs.h: Fix lint error 
`make lint` reports errors and warnings

Solve the next errors:
- SPACE_BEFORE_TAB
- SPACING

BUG = N/A
TEST = Build Compulab Intense-PC with secure oprom enabled

Change-Id: Ic7062e07a76bf95fe8e2e849f1d14342c9081a23
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49938
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-01 08:46:11 +00:00
Arthur Heymans
5fc2bed629 drivers/intel/fsp2_0: Use CBFS_MCACHE when coreboot tears down CAR 
TESTED on ocp/tiogapass.

Change-Id: I30560149eeaec62af4c8a982815618be5546531c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-01 08:45:37 +00:00
Arthur Heymans
129ed0a264 soc/intel/xeon_sp: Use native CAR teardown 
This cleans up the postcar frame setup, which now gets used instead of
just going with TempRamExit MTRR's.

Note that ramstage CPU init sets up different final MTRRs anyway.

TESTED on ocp/deltalake and ocp/tiogapass.

Change-Id: I756c2d479fef859a460696300422f08013a300f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-01 08:45:15 +00:00
Arthur Heymans
98cc7830e7 drivers/intel/fsp2_0: Use coreboot postcar with FSP-T 
Allow platforms to use the coreboot postcar code instead of calling
into FSP-M TempRamExit API.

There are several reasons to do this:
- Tearing down CAR is easy.
- Allows having control over MTRR's and caching in general.
- The MTRR's set up in postcar be it by coreboot or FSP-M are
  overwritten later on during CPU init so it does not matter.
- Avoids having to find a CBFS file before cbmem is up (this
  causes problems with cbfs_mcache)

Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-01 08:45:05 +00:00
Michael Niewöhner
33c0aac3b6 soc/intel/*: drop incomplete and unneeded check for DMI SRLOCK 
Before enabling IO decode ranges, current code checks if the DMI SRLOCK
is set to prevent inconsistencies between LPC PCI cfg registers and LPC
DMI registers, when the latter are locked.

DMI SRLOCK only applies to PCHs with on-package DMI, but not to PCH-H,
PCH-S and others with discrete PCH packages. So this check is at least
incomplete.

Further, the lock gets applied by FSP and gets reset on a warm reset.
Thus, there is no case where the lock would be already set at the
places where the DMI registers get written currently.

Drop the checks for the reasons mentioned above.

Change-Id: I59554ce96bce7f7d1a4ba9b098be9e8466c68eac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49885
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-31 19:27:55 +00:00
Felix Held
d8ab828e5b soc/amd/common/block/aoac: expand acronym in Kconfig help text 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I08ad12cd7c8de7a7f170d3dc76c8942131687301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50163
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-31 18:48:06 +00:00
Kyösti Mälkki
255b6f8646 util/vboot_lib: Add description.md 
Fixes lint-stable-025 error.

Change-Id: I4aa2b2a2ffca69f894a23d7487926016830c9e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50114
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-31 11:15:59 +00:00
Angel Pons
2399adaeb0 mb/emulation/qemu-q35: Use common MADT 
Select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT and drop the `acpi_fill_madt`
function definition, which is redundant. Tested, still boots to payload.

Change-Id: I6ba448f264a478e7ef060ea1dfbf5016a310d528
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-01-31 11:12:32 +00:00
Angel Pons
cba669cd95 mb/emulation/qemu-q35: Define and use MMCONF_BUS_NUMBER 
Also refactor the machine type checks to avoid code duplication.

Tested, still boots to payload with 256, 128 and 64 busses.

Change-Id: Ib394ba605bbfeee75aa645e989c23034cceff348
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50025
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-31 11:12:25 +00:00
Felix Held
338d670beb soc/amd/cezanne/Kconfig: select common PSP gen2 support 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6068e8b9eb210ce4907fda09208e66e380842de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-31 01:13:04 +00:00
Felix Held
84439c26d8 soc/amd/picasso/psp: move soc_get_mbox_address to common PSP gen2 code 
The function to get the PSP mailbox address is the same on Picasso and
Cezanne, so move it to the common PSP generation 2 code. The function is
only used in the same compilation unit, but it can't be marked as static
due to the function prototype in amdblocks/psp.h that is still needed
for Stoneyridge.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieea91ef76523d303f948d29ef48e3b2e56293f26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-31 01:12:37 +00:00
Felix Held
31fdefe584 soc/amd/stoneyridge/psp: fix check of MSR_PSP_ADDR contents 
TEST=Checked documentation, but not verified on hardware.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06399ac9cb9c90701dbcba71cbc808a0d7e6ea0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-31 01:12:18 +00:00
Felix Held
4836889249 soc/amd/picasso/psp: fix check of MSR_PSP_ADDR contents 
If MSR_PSP_ADDR is uninitialized, it's all zeros and not all ones.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iecd3039f63f9d0cb75fe3cb37aee92ba65bbbb50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-31 01:09:34 +00:00
Felix Held
ee04881360 soc/amd/*/psp: move MSR_CU_CBBCFG to common and rename to MSR_PSP_ADDR 
TEST=Checked that the MSR is the same for Stoneyridge, Picasso and
Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id15715ed1c17f4fc475985dcb1c31a83713ee65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-31 01:09:18 +00:00
Felix Held
5ddcfe5ec1 soc/amd/stoneyridge/southbridge: move PSP BAR hide bit to its register 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9838e2433004686e3ea82724c55066bcee1f019
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-31 01:09:04 +00:00
Felix Held
abde3ff503 soc/amd/cezanne: add soc/cpu.h with CPUID define for Cezanne A0 stepping 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b6d8b0c5ff5e58f6ab487d9fe724534f0108f83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-31 01:08:46 +00:00
Angel Pons
fd3df8e24b sb/intel/ibexpeak: Drop invalid ME finalisation function 
Was copied from bd82x6x and none of the PCI IDs matches that of Ibex
Peak (PCI_DID_INTEL_IBEXPEAK_HECI1 = 0x3b64). Remove the code. This
allows dropping the me_8.x.c dependency, which never made sense.

Change-Id: I54df1e080048c0599dbee687ec617fb724cb6634
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-01-30 23:25:02 +00:00
Angel Pons
02414f8d57 soc/intel/broadwell/pch: Drop some config_of uses 
There's no need to die here. Also simplifies merging with Haswell.

Change-Id: I3d4bc79b32279180442dbc82126e297f11f1fb80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-01-30 23:15:54 +00:00
Angel Pons
0a45b40fb2 soc/intel/broadwell: Move ramstage.c to PCH scope 
The remaining code in this file is PCH-specific.

Change-Id: I0e4924e680db9c25aeb222bdd478b3282a77b34f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49946
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:15:23 +00:00
Angel Pons
e780d980e9 soc/intel/broadwell: Make broadwell_init_pre_device static 
This small function is only used in one place.

Change-Id: Ieccdca60fb7837b6406a6b2fd7ebae86958a1afe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49945
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:14:59 +00:00
Angel Pons
9849488da1 soc/intel: Replace SA_PCIEX_LENGTH Kconfig options 
Use the existing `MMCONF_BUS_NUMBER` and `MMCONF_LENGTH` symbols.

Change-Id: I88dcc0d5845198f668c6604c45fd869617168231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-01-30 23:14:08 +00:00
Angel Pons
90be7544e4 device: Drop mmconf_resource_init function 
All uses of `mmconf_resource_init` have been replaced in previous
patches with `mmconf_resource`, which uses Kconfig symbol values.

Change-Id: I4473268016ed511aa5c4930a71977e722e34162a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-01-30 23:13:22 +00:00
Angel Pons
a6b0922aa1 nb/intel/i945: Define and use MMCONF_BUS_NUMBER 
Change-Id: I5c75409fd3b7b018e402c471cbd856eca20278b7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49757
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:13:05 +00:00
Angel Pons
1ac6f8b804 nb/intel/gm45: Define and use MMCONF_BUS_NUMBER 
Change-Id: I635f3615f566502f79bbd81f9f743ce63bba3b1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49758
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:12:54 +00:00
Angel Pons
bbc80f4405 nb/intel/x4x: Define and use MMCONF_BUS_NUMBER 
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Moreover, the ASL reservation for MMCONFIG was only for 64 busses.

Change-Id: I7366a5096aacd92401535be020358447650b4247
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:12:44 +00:00
Angel Pons
1318ab475d nb/intel/pineview: Define and use MMCONF_BUS_NUMBER 
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.

Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:12:32 +00:00
Angel Pons
b274ec73ab nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhere 
Bootblock enabling needs some special handling. Also, the definition of
the `get_pcie_bar` function is incorrect for Ironlake, so remove it.

With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work.
However, it has not been tested. Using 256 busses should still work.

Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:12:23 +00:00
Angel Pons
10f9b83f53 nb/intel/sandybridge: Define and use MMCONF_BUS_NUMBER 
Change-Id: Id88c18129bb773d979ad84bd0bb47188d74d4bc4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49762
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:11:36 +00:00
Angel Pons
32770f840d nb/intel/haswell: Define and use MMCONF_BUS_NUMBER 
Change-Id: I0d6338f763a78895b1ae14d1ab68253851b6c283
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49763
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:11:15 +00:00
Angel Pons
9debbd65af soc/intel/broadwell: Define and use MMCONF_BUS_NUMBER 
Note that ACPI MCFG generation reported too many busses.

Change-Id: I5acd26bac675cc818df46f60887f90b76f4580a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50034
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:10:43 +00:00
Angel Pons
33bededa11 soc/intel/broadwell: Use common SMBus code 
Change-Id: I74b21bfde4b76ccb0d432b00c25095f708b1d761
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50030
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:10:33 +00:00
Angel Pons
50632878bf device/Kconfig: Introduce MMCONF_LENGTH 
This is necessary because ASL Memory32Fixed values cannot contain
operations, even if they can be evaluated to constants. Add a sanity
check in pci_mmio_cfg.h to ensure consistency with MMCONF_BUS_NUMBER.

Change-Id: I8f0b5edf166580cc12c1363d8d6b6ef0f2854be9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50033
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:10:22 +00:00
Angel Pons
67df3ff800 soc/intel/{baytrail,broadwell} Fix building with refcode blobs 
Because the refcode blobs are not redistributable, refcode.c is not
build-tested. Commit 6271dd8459 (soc/intel/baytrail,broadwell: Use
resume_from_stage_cache()) broke building with refcode blobs. Fix a
variable redeclaration error by swapping the order of the code, and
use consistent names for the variables.

Change-Id: Ic8dda8d35086d977b536686e8c80b7961c37860c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-01-30 23:10:05 +00:00
Angel Pons
ec99cd9112 sb/intel/bd82x6x: Clean up early_thermal.c 
Use proper types in readXp functions, define `PCH_THERMAL_DEV`, clean up
comments a bit, and use `RCBA32_AND_OR` instead of read32/write32.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: I95e054d6e52706e06e313068e61484f6cb9a64e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50038
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:08:06 +00:00
Angel Pons
ee7fb34dcb nb/intel/ironlake: Use RCBA macros 
Use defined RCBAx macros over readX/writeX calls.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I87cae75268ef5f329001706e4771e98653d40cd1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50037
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:07:55 +00:00
Patrick Georgi
60f5328c7d libpayload/arm*: Add 64bit memory access primitives 
Add read64 and write64 for consistency with x86.

BUG=b:178785769

Change-Id: I342e3a23201d0b804ea5ecfe47ee3e4bb516de4c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2021-01-30 20:17:47 +00:00
Zheng Bao
adac6f40f2 mb/amd/majolica: Add an empty bootblock function to handle GPIO 
Change-Id: I35da3812a424ea1beef86d043a756a87e6afdaa3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50117
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 17:56:15 +00:00
Angel Pons
27ee72f117 util/testing/Makefile.inc: Fix up license header 
Drop unnecessary leading empty lines in comment.

Change-Id: Idc0f9d1548336dc2df2d59b18af8d717efa60b68
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
 2021-01-30 17:45:16 +00:00
Zheng Bao
c1363d7541 mb/amd/majolica: Add an empty function of mainboard bootblock 
Change-Id: I985405b51c81d1e5a3a593bfb759e9850beb2244
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-01-30 17:43:58 +00:00
Felix Held
889959890c drivers/intel/fsp2_0: factor out and improve UPD signature check 
In case of a mismatch print both the UPD signature in the FSP and the
expected signature and then calls die(), since it shouldn't try calling
into the wrong FSP binary for the platform.

Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I469836e09db6024ecb448a5261439c66d8e65daf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-01-30 17:20:50 +00:00
Kyösti Mälkki
564b4c5453 soc/amd,intel: Drop leftover GNVS includes 
Change-Id: Ia55d53a9a40846db335aabbe4df8e87f6172f712
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-30 17:19:03 +00:00
Felix Held
a21690ba12 soc/amd/stoneyridge/southbridge: replace southbridge prefix with fch 
This aligns the function names with Picasso and Cezanne. Also move the
fch_* functions in the header file in the order they get called.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49db8021edae5e537f043bf52eea1be54dc46eca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-01-30 17:17:48 +00:00
Felix Held
ffc87e9cbe soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls 
Cezanne doesn't have ACPI support yet, but in this case the function
always returns 0, so it can already be used.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1f5e1f31bf1e52988fcef90daf7b93169e21cbb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50126
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 17:17:24 +00:00
Felix Held
ac86cf33bf soc/amd/picasso/chip: add missing acpi/acpi.h include 
acpi_is_wakeup_s3() is defined in acpi/acpi.h

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53916cd15bb28484eb06be4d43f26152de159391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50125
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 17:17:01 +00:00
Subrata Banik
349b64f37a soc/intel/common/block: Create PCIE related macros 
Add generic PCIE RP related macros for SoC layer to use.

Change-Id: I84d02daded5cfe11120f099dc80c00ac0ec795f1
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-01-30 14:38:53 +00:00
Subrata Banik
0b53d8b883 soc/intel/alderlake: Remove pch.h from SoC directory 
Remove unnecessary include of soc/pch.h from
- bootblock/pch.c
- bootblock/report_platform.c
- bootblock/uart.c

Define PCIE_CLK_XXX macro inside chip.h for mb/devicetree.cb to
consume.

Change-Id: Ic08ef586d4590462434ba2c64e21dd802ccc6800
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50132
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 14:38:38 +00:00
Subrata Banik
1d18c8e3c8 mb/intel/adlrvp: Remove unnecessary whitespace 
Change-Id: I46af3e789de10ca6951b9e17f286c094c08a477f
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-01-30 14:38:24 +00:00