soc/intel/broadwell: Define and use MMCONF_BUS_NUMBER
Note that ACPI MCFG generation reported too many busses. Change-Id: I5acd26bac675cc818df46f60887f90b76f4580a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50034 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -77,9 +77,11 @@ config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config MMCONF_BUS_NUMBER
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default 64
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config VGA_BIOS_ID
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string
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default "8086,0406"
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@@ -25,7 +25,8 @@
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
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MCFG_BASE_ADDRESS, 0, 0, 255);
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CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
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CONFIG_MMCONF_BUS_NUMBER - 1);
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return current;
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}
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@@ -178,7 +178,7 @@ Device (PDRC)
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Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE)
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Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE)
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Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE)
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Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
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Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
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Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE)
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Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE)
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})
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@@ -1,28 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/bootblock.h>
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#include <assert.h>
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/systemagent.h>
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static uint32_t encode_pciexbar_length(void)
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{
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switch (CONFIG_MMCONF_BUS_NUMBER) {
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case 256: return 0 << 1;
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case 128: return 1 << 1;
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case 64: return 2 << 1;
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default: return dead_code_t(uint32_t);
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}
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}
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void bootblock_early_northbridge_init(void)
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{
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uint32_t reg;
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/*
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* The "io" variant of the config access is explicitly used to
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* setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
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* true. That way all subsequent non-explicit config accesses use
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final
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* assumption is that no assembly code is using the
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* The "io" variant of the config access is explicitly used to setup the
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* PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
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* subsequent non-explicit config accesses use MCFG. This code also assumes
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* that bootblock_northbridge_init() is the first thing called in the non-asm
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* boot block code. The final assumption is that no assembly code is using the
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* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
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*/
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reg = 0;
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pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
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reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
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const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
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pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, 0);
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pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
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}
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@@ -3,9 +3,6 @@
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#ifndef _BROADWELL_IOMAP_H_
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#define _BROADWELL_IOMAP_H_
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#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
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#define MCFG_BASE_SIZE 0x4000000
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#define MCH_BASE_ADDRESS 0xfed10000
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#define MCH_BASE_SIZE 0x8000
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@@ -15,7 +15,7 @@ void broadwell_fill_pei_data(struct pei_data *pei_data)
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pei_data->pei_version = PEI_VERSION;
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pei_data->board_type = BOARD_TYPE_ULT;
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pei_data->usbdebug = CONFIG(USBDEBUG);
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pei_data->pciexbar = MCFG_BASE_ADDRESS;
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pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
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pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE;
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pei_data->ehcibar = EARLY_EHCI_BAR;
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pei_data->xhcibar = EARLY_XHCI_BAR;
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