soc/intel/broadwell: Define and use MMCONF_BUS_NUMBER

Note that ACPI MCFG generation reported too many busses.

Change-Id: I5acd26bac675cc818df46f60887f90b76f4580a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50034
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-01-28 12:42:53 +01:00
parent 33bededa11
commit 9debbd65af
6 changed files with 26 additions and 20 deletions

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@@ -77,9 +77,11 @@ config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
config MMCONF_BUS_NUMBER
default 64
config VGA_BIOS_ID
string
default "8086,0406"

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@@ -25,7 +25,8 @@
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
MCFG_BASE_ADDRESS, 0, 0, 255);
CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}

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@@ -178,7 +178,7 @@ Device (PDRC)
Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE)
Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE)
Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE)
Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE)
Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE)
})

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@@ -1,28 +1,34 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
#include <assert.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
default: return dead_code_t(uint32_t);
}
}
void bootblock_early_northbridge_init(void)
{
uint32_t reg;
/*
* The "io" variant of the config access is explicitly used to
* setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
* true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
* The "io" variant of the config access is explicitly used to setup the
* PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
* subsequent non-explicit config accesses use MCFG. This code also assumes
* that bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using the
* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
reg = 0;
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, 0);
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
}

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@@ -3,9 +3,6 @@
#ifndef _BROADWELL_IOMAP_H_
#define _BROADWELL_IOMAP_H_
#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define MCFG_BASE_SIZE 0x4000000
#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE 0x8000

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@@ -15,7 +15,7 @@ void broadwell_fill_pei_data(struct pei_data *pei_data)
pei_data->pei_version = PEI_VERSION;
pei_data->board_type = BOARD_TYPE_ULT;
pei_data->usbdebug = CONFIG(USBDEBUG);
pei_data->pciexbar = MCFG_BASE_ADDRESS;
pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE;
pei_data->ehcibar = EARLY_EHCI_BAR;
pei_data->xhcibar = EARLY_XHCI_BAR;