9debbd65af
Note that ACPI MCFG generation reported too many busses. Change-Id: I5acd26bac675cc818df46f60887f90b76f4580a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50034 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
103 lines
2.9 KiB
C
103 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <acpi/acpigen.h>
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#include <arch/ioapic.h>
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#include <arch/smp/mpspec.h>
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#include <cbmem.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <device/pci_ops.h>
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#include <cpu/x86/smm.h>
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#include <console/console.h>
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#include <types.h>
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#include <string.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/turbo.h>
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#include <soc/acpi.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/systemagent.h>
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#include <soc/intel/broadwell/chip.h>
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
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CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
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CONFIG_MMCONF_BUS_NUMBER - 1);
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return current;
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}
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static unsigned long acpi_fill_dmar(unsigned long current)
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{
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struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
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const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
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const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
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const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
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const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
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/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
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const bool emit_igd =
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igfx_dev && igfx_dev->enabled &&
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gfxvtbar && gfxvten &&
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!MCHBAR32(GFXVTBAR + 4);
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/* First, add DRHD entries */
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if (emit_igd) {
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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/* VTVC0BAR has to be set, enabled, and in 32-bit space */
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if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current,
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DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
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current += acpi_create_dmar_ds_ioapic(current,
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2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
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size_t i;
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for (i = 0; i < 8; ++i)
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current += acpi_create_dmar_ds_msi_hpet(current,
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0, PCH_HPET_PCI_BUS,
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PCH_HPET_PCI_SLOT, i);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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/* Then, add RMRR entries after all DRHD entries */
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if (emit_igd) {
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const unsigned long tmp = current;
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current += acpi_create_dmar_rmrr(current, 0,
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sa_get_gsm_base(), sa_get_tolud_base() - 1);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_rmrr_fixup(tmp, current);
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}
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return current;
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}
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unsigned long northbridge_write_acpi_tables(const struct device *const dev,
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unsigned long current,
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struct acpi_rsdp *const rsdp)
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{
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/* Create DMAR table only if we have VT-d capability. */
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const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
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if (capid0_a & VTD_DISABLE)
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return current;
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acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
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printk(BIOS_DEBUG, "ACPI: * DMAR\n");
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acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
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current += dmar->header.length;
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current = acpi_align_current(current);
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acpi_add_table(rsdp, dmar);
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return current;
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}
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