sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
43,043 Commits 47 Branches 30 Tags
750200020ab82f3be2bfda959bd3280a46b7a1cc
Commit Graph

43043 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Tony Huang
b37f2e9902 mb/google/puff/var/dooly: update USB2 type-c strength 
Based on USB DB report.

BRANCH=puff
BUG=b:163561808
TEST=build and measure by EE team.

Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
 2020-11-22 22:30:03 +00:00
Martin Roth
08b862ef47 nb/amd/pi: Remove 00660F01 directory & files 
These files are not used by any platform, so remove them.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I75651d2cc53fc5a3cb3233686ad66881d129312d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:29:49 +00:00
David Wu
6be3352e98 mb/google/volteer: Remove unused devices for terrador and todor 
Remove the following devices
- Goodix Touchscreen
- SAR0 Proximity Sensor

BUG=b:173480406
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47690
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:29:17 +00:00
Elyes HAOUAS
1ba663ce0a crossgcc: Upgrade nasm to version 2.15.05 
Changes (https://nasm.us/doc/nasmdocc.html):
Version 2.15.05:
Correct %ifid $ and %ifid $$ being treated as true.
Add --reproducible option to suppress NASM version numbers and
timestamps in output files.

Version 2.15.04:
Correct the encoding of the ENQCMDS and TILELOADT1 instructions.
Fix case where the COFF backend (the coff, win32 and win64 output
formats) would add padding bytes in the middle of a section if a
SECTION/SEGMENT directive was provided which repeated an
ALIGN= attribute. This neither matched legacy behavior, other
backends, or user expectations.
Fix SSE instructions not being recognized with an explicit memory
operation size (e.g. movsd qword [eax],xmm0).

Change-Id: I3f9aa8e743f2dc50fce1ce68718c0ae17209a509
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44694
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:28:16 +00:00
Elyes HAOUAS
274c3faf09 crossgcc: Upgrade IASL to version 20200925 
This release added support for SMBus predefined names: _SBA, _SBI, _SBR,
_SBT and _SBW.

CB:44507 and CB:41735 needs this version.

Change log: https://acpica.org/node/184

Change-Id: I3559e5bd884db4dccdaa5ac7edba4faf57da7930
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-11-22 22:28:03 +00:00
Frans Hendriks
c248382d52 vendorcode/eltan/security: Add dependency for menu items 
Subitem for VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT are
always displayed.

Add dependency and display these items when feature is enabled only.

Tested on Facebook FBG1701.

Change-Id: I51e47efddbcf51d87439bec33b85432da56fa4c6
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:27:43 +00:00
Patrick Rudolph
d8d8be1a6a drivers/tpm: Move PPI stub 
As preparation to a full PPI implementation move the acpi code out
of the pc80/tpm/tis driver into the generic tpm driver folder.

This doesn't change any functionality.

Change-Id: I7818d0344d4a08926195bd4804565502717c48fa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:27:29 +00:00
Frans Hendriks
ac7f461d8d mb/facebook/fbg1701/Kconfig: Add dependency 
VENDORCODE_ELTAN items are only used when USE_VENDORCODE_ELTAN is enabled.

Add dependency of USE_VENDORCODE_ELTAN.

Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:26:51 +00:00
Arthur Heymans
02dec12629 soc/intel/xeon_sp: Work around FSP-T not respecting its own API 
The CPX FSP-T does not respect the FSP2.x spec and uses registers where
coreboot has its initial timestamp stored.

If the initial timestamp is later than some other timestamps this
messes up the timestamps 'cbmem -t' reports as it thinks they are a
result from a timestamp overflow (reporting that it took 100k years to
boot).

TEST: The ocp/deltalake boots within the span of a lifetime.

Change-Id: I4ba15decec22cd473e63149ec399d82c5e3fd214
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:26:25 +00:00
Sheng-Liang Pan
832dd4388a mb/google/octopus: fix droid lte sku load specific wifi sar value 
This CL add droid lte sku 37 38 39 40 to load wifi_sar-droid.hex.

BUG=none
BRANCH=octopus
TEST=emerge-octopus coreboot

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I55dda85b8f3e664d97834b712a2c6a48d1434010
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47697
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:26:08 +00:00
Arthur Heymans
b54212109e cpu/amd/microcode: Remove dead Makefile 
Change-Id: If9d1e28ac50b8ca227b2c09dbbfdd3c9b60aca6a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:25:42 +00:00
Arthur Heymans
8461cec76c soc/intel/block/pmclib.c: Properly guard apm_control() 
This function is only properly implemented with SMM support.

Change-Id: I9e0fc7433a9226825f5ae4903c0ff2e0162d86ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:25:23 +00:00
Arthur Heymans
f2baae3735 soc/intel/common/pmc.c Don't implement a weak function that dies 
Buildtime failures are better than runtime failures.

Change-Id: I5fe4c86a13dbabb839977010f129419e337e8281
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:25:10 +00:00
Arthur Heymans
1ae8cd1064 soc/intel/block/pmc: Only include the PCI driver when it is not hidden 
On more recent Intel platforms FSP-S hides the PMC PCI device and the
driver is broken for those devices so don't include it at all.

Change-Id: I784be250698ec1c1e9b3b766cf1bcca55730c021
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:25:03 +00:00
Arthur Heymans
08c646c060 soc/intel/block/pmc: Move pmc_set_acpi_mode() to pmc_lib.c 
pmc.c mostly contains a PCI driver, while this function just calls
into SMM.

Change-Id: I9a93a5079b526da5d0f95f773f2860e43b327edf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:24:54 +00:00
Mariusz Szafranski
778c4f8c96 MAINTAINERS: update maintainers of Intel Denverton-NS SoC 
Change-Id: Ifdb24f9566b53af6c23b4cd4adba0c1876e4fc9d
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian <d.guckian20@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-11-22 22:24:41 +00:00
Elyes HAOUAS
e49856dfa8 soc/intel/denverton_ns: Convert to ASL 2.0 syntax 
Change-Id: I261add8142c3192ab944845e8e1a362a3aca00c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
 2020-11-22 22:24:19 +00:00
David Wu
d3a1560609 mb/google/volteer/var/voema: Update gpio and devicetree settings 
Based on latest schematic and gpio table of voema, update gpio and
devicetree settings for voema Proto.

BUG=b:169356808
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I719a9948ed0d60e1de5368e096ff60c2345803b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-11-22 22:24:12 +00:00
Martin Roth
c681a82657 cpu/amd/pi: Remove unused cpu code 00660F01 
Remove the processor directory and references to the Kconfig symbol.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I403a453362fd76d6ef2a5b75728a362efa4f2491
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:23:22 +00:00
Frans Hendriks
7e3bf0c5dd mb/facebook/fbg1701: Add VBOOT support 
Add VBOOT support.

Disable USE_VENDOR_ELTAN when VBOOT is enabled.
Add FMD file and split binary into RW and RO region settings.

Tested on Facebook FBG1701

Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
 2020-11-22 22:22:46 +00:00
Matt DeVillier
3d62781acb drivers/i2c/hid: Use ACPI device name if provided by config 
Follow model of drivers/i2c/generic and use user-supplied device
name if specified in the chip config.

Change-Id: Ia783bac2797e239989c03a3421b9293a055db3d0
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47782
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:22:06 +00:00
Matt DeVillier
86dce8fa75 drivers/i2c/generic: Only write DDN field if description not empty 
DDN field isn't required, no point in writing an empty string to it.

Change-Id: Ifea6e48c324598f114178e86a79f519ee35f5258
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47781
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:22:00 +00:00
Paul Menzel
9226fe9aee Documentation: Mention newer Intel μ-code updates in 4.13 release notes 
Start a new section *Notes* for these kind of information.

Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47762
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:21:29 +00:00
Eric Lai
f9ed4d20f1 drivers/i2c: Add a driver for Semtech SX9324 
This adds a new driver for the SX9324 proximity detector device.
Follow SX9324 datasheet Rev3.

BUG=b:172397658
BRANCH=zork
TEST=Test sx9324 is working as expected.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifd582482728a2f535ed85f6696b2f5a4529ba421
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47640
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:20:33 +00:00
Angel Pons
c930c87998 Doc/releases/checklist.md: Fix up URLs 
Use angle brackets so that they appear as links, and update a link to a
Gerrit change to use the current format.

Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47812
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:19:58 +00:00
Angel Pons
5ea7bb74bd Doc/releases/checklist.md: Add reminder to unpack relnotes 
Explicitly add this easy-to-forget step. Also add a missing period.

Change-Id: Iaf13155fcc8a70f3565fb2404cef886524fa5161
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47811
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:19:48 +00:00
Angel Pons
2687d37a3c payloads/external: Fix up SPDX license headers 
Remove copyright notices and other unnecessary churn.

Change-Id: Ie69cc121d2b6eed95aa3cbaa7215d61880148858
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47815
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:19:19 +00:00
Angel Pons
6d4de7eef9 payloads/external/Makefile.inc: Fix SeaBIOS option regressions 
Commit 14ca740719 (Makefile.inc: Move adding SeaBIOS cbfs config files)
introduced various regressions that were not spotted during review.

TEST=Building with SEABIOS_THREAD_OPTIONROMS is working properly again.

Change-Id: I4de0b11747e3df8dd31a85160add129d8cc6bd8a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47814
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-22 22:18:54 +00:00
Maxim Polyakov
0fcd37172f mb/kontron: Add Kontron mAL10 COMe module support 
This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.

Working:
  - UART console and I2C on Kontron kempld;
  - USB2/3
  - Ethernet controller
  - eMMC
  - SATA
  - PCIe ports
  - IGD/DP
  - SMBus
  - HWM

Not tested:
  - IGD/LVDS
  - SDIO

TODO:
  - HDA (codec IDT 92HD73C1X5, currently disabled)

Tested payloads:
  - SeaBIOS
  - Tianocore, UEFIPayload - without video, EFI-shell in console only

Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)

Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:18:22 +00:00
Frans Hendriks
0948b363b0 soc/intel/braswell/bootblock/bootblock.c: Report the FSP-T output 
Report the FSP temporary RAM location

Tested on Facebook FBG1701

Change-Id: Ia2ce48f7a7948d1fe51ad1ca33b8fb385674cb41
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:17:53 +00:00
Frans Hendriks
c022a79503 drivers/intel/fsp1_1: Add function to report FSP-T output 
This allows to compare the FSP-T output in %ecx and %edx to coreboot's
CAR symbols.

Tested on Facebook FBG1701

Change-Id: Ice748e542180f6e1dc1505e7f37b6b6c68772bda
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:17:43 +00:00
Frans Hendriks
335eb1219c src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only 
Whole car region is cleared, while only small part needs to be done.

Clear .bss area only

Tested on Facebook FBG1701

Change-Id: I021c2f7d3531c553015fde98d155915f897b434d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-22 22:17:22 +00:00
Karthikeyan Ramasubramanian
f752fc6546 mb/google/sarien: Configure IRQs as level triggered for HID over I2C 
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx

BUG=b:172846122
TEST=./util/abuild/abuild

Change-Id: I27c485c9c8c5d47a44fc050d8cf12c553bffd01e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-11-22 22:17:07 +00:00
Tim Wawrzynczak
f61011a56f mb/google/brya: Add new google brya mainboard 
This commit is a stub for brya, which is a an Intel Alder Lake-P
reference platform.

BUG=b:173562731
TEST=util/abuild/abuild -p none -t google/brya -a -c max

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia34130ff92a0a07063cb8e80527204b3a80184a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2020-11-22 22:16:27 +00:00
Furquan Shaikh
6c8ba9b9ae vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFS 
If AGESA is added as a raw binary (and not a stage), then cbfstool
does not perform relocation. In this case, it should be added only to
COREBOOT (i.e. default) CBFS since the binary needs to be present only
in one specific location that is present in the default CBFS.

Change-Id: I7a7edc217663f9d1d36b05308bbd35f56a28b9b1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:15:07 +00:00
Angel Pons
121d2de18d util/inteltool/ivy_memory.c: Do not rely on MR0 values 
MR0 may not always be programmed in the training result registers. Thus,
do not rely on its values. Also account for per-channel differences.

Change-Id: Iaf3b545ea55735b46caf1bd62d5859f2b3efa159
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-22 22:14:26 +00:00
Angel Pons
0b6ab953f3 util/inteltool/ivy_memory.c: Properly mask tAONPD 
This field is only 4 bits wide.

Change-Id: I2cb746e98176d58fc5be423e18babdaa8801b096
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:14:15 +00:00
Angel Pons
4f86d63006 nb/intel/sandybridge: Clean up COMPOFST1 logic 
This register needs to be updated differently depending on the CPU
generation and stepping. Handle this as per reference code. Further,
introduce a bitfield for the register to make the code easier to read.

Change-Id: I51649cb2fd06c5896f90559f59f25d49a8e6695e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:14:03 +00:00
Angel Pons
2921cbf277 nb/intel/sandybridge: Correct get_COMP2 function 
Values differ between Sandy and Ivy Bridge. Remove the lookup table,
since it contains duplicated values and is hard to see which values
correspond to which frequencies. New values come from reference code.

Change-Id: I3b28568f0053f1b39618e16bdffc24207547d81f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:13:55 +00:00
Angel Pons
2a7d752aaa nb/intel/sandybridge: Rename and refactor discover_timC_write 
This is actually aggressive write training, similar to aggressive read
training. Rename it accordingly and refactor it to improve clarity.

Enabling IOSAV_n_SPECIAL_COMMAND_ADDR optimizations must only be done
for later Ivy Bridge steppings. Therefore, guard the code accordingly.

Change-Id: Ia3331b95c265113d94cb5d66c57a97cb77fc3dc9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:13:45 +00:00
Angel Pons
9fbb1b096f nb/intel/sandybridge: Only use write Vref if supported 
Only some Ivy Bridge SKUs support write Vref control.

Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:13:28 +00:00
Angel Pons
09fc4b90eb nb/intel/sandybridge: Refine power-down mode logic 
When memory is running at fast frequencies, power-down modes can lessen
system stability. Check tXP and tXPDLL values and use safer power down
modes if their values are high. Do not use APD with DLL-off on mobile:
vendor firmware does not use it, and it can influence system stability.

Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:13:18 +00:00
Angel Pons
2ad03a43ec nb/intel/sandybridge: Lower tPRPDEN to 1 
This is the default value, and matches what vendor firmware does.

Change-Id: Id0c9758a845d711a87c4b06f89fa0926ae658e02
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:13:01 +00:00
Angel Pons
1146332b9c nb/intel/sandybridge: Increase tRWDRDD with fast RAM 
This has been reported to increase stability, and vendor BIOS also does
the same.

Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:12:51 +00:00
Angel Pons
08f749d5f6 nb/intel/sandybridge: Rename and clean up discover_edges_write 
This is actually an (incomplete) aggressive read training algorithm.
Rename functions and variables accordingly, and tidy up declarations.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I8a4900f8e3acffe4e4d75a51a2588ad6b65eb411
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:12:21 +00:00
Angel Pons
801a5cbaac nb/intel/sandybridge: Relocate PREA-ACT-RD sequence 
Tested on Asus P8H61-M PRO, still boots.

Change-Id: Ie5e243380d940ca89857b230e15091ac01fde928
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:11:58 +00:00
Angel Pons
c674223fd4 nb/intel/sandybridge: Remove spurious writes to IOSAV BW mask 
The byte-wise error mask only needs to be set for certain corner cases
in read MPR training. Thus, minimize writes to this register.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I0bb8d99ad60c4964f896d303878e5982ae1dcdbe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:11:37 +00:00
Angel Pons
4c76d25717 nb/intel/sandybridge: Drop precharge function 
This is a copy of `find_predefined_pattern` without any effect.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: Ieb72066ca25b40b6e60f04e6c4097a0ccc2a56b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 22:10:50 +00:00
Felix Singer
c39d11cec0 mb/*: Use ACPI_DSDT_REV_2 instead of hard-coded value 
Change-Id: I6c5b86c348386aa17ee42bdaf34aa388fe6207f9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-11-22 22:03:22 +00:00
Angel Pons
a1f1714ca5 nb/intel/sandybridge: Clarify register write 
It is necessary to program this register before doing an I/O reset.

Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-11-22 20:41:08 +00:00