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21100 Commits

Author SHA1 Message Date
Richard Spiegel
4bb706555e vendorcode/amd/pi/00670F00: Control which procedure builds 
Vendor code is compiled as a library, thus the whole library is included
into the final image. However, not all procedures are required, they are
there because original AGESA code had them. We cannot remove them, in order
to facilitate porting of fixed AGESA code. Therefor add #if throughout the
code to allow the control if unneeded procedures will be build.

BUG=b:78610011
TEST=Build and boot grunt; build kahlee and gardenia.

Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26135
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-09 10:12:33 +00:00
Richard Spiegel
9c1dc7cbe1 vendorcode/amd/pi/00670F00: Remove unneeded includes 
Vendor code has several headers included into source code that are not
needed in order to build them. Remove unneeded #include. This is part of
controlling the build of unneeded procedures within vendor code.

BUG=b:78610011
TEST=Build grunt.

Change-Id: Id7d451b6be564632836fc64fd343131edb85183a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2018-05-09 10:12:24 +00:00
Elyes HAOUAS
ae27430a3c mb/gizmosphere: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I75258ecc5f3881012c3f767c8b970a1f10c6abbd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-09 10:09:44 +00:00
Elyes HAOUAS
547c5aa2b5 mb/elmex: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: If4ec2e2e7cca8d8f3e5abfd9cd204f86e367b44a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-09 10:09:39 +00:00
Elyes HAOUAS
c390e7e605 mb/esd: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I5928e871b8e9ba5964c02fbabb7a9d8dc9ecc0a8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-09 10:09:35 +00:00
Harsha Priya
78ccdbf15b mainboard/google/eve: Add subsystem_id 
This patch adds subsystem_id for eve as 0x006B. The value
is set in nhlt structure which will be used by endpoints as well.

Change-Id: Id6910678c4d6e92ed45c776f174855efd26f9e27
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2018-05-09 10:08:41 +00:00
Harsha Priya
5c31511f35 lib/nhlt: add support for passing subsystem_id to endpoint's structure 
This patch adds subsystem_id to nhlt structure whose value is
passed on to the endpoint's structure. Its default value is
retained to be NHLT_SSID.

Change-Id: Iad53f27e958f50e02e928cd8fa60d8397ca0eb06
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26046
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-09 10:06:04 +00:00
Kyösti Mälkki
cebb684417 console: Skip non-BSP printk() earlier 
Fix regression after commit:
  6032018 console: only allow console messages after initialization

Bail out early on AP CPUs, this avoids use of CAR_GLOBAL when
we have SQUELCH_EARLY_SMP=y.

Change-Id: I506c5fbec43a6eb6f6d9362d62a040def9e1e7bb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2018-05-09 05:21:21 +00:00
Furquan Shaikh
f5b7e80c22 mb/google/poppy/variants/nami: Add support for getting OEM name from CBFS 
This change:
1. Allows mainboard to add OEM table to CBFS
2. Provides mainboard specific smbios_mainboard_manufacturer that reads
OEM ID from EC using CBI and compares it against the OEM ID in CBFS
table to identify the right OEM string.

BUG=b:74617340

Change-Id: Iff54b12745de3efa7be0801c9a3a9f2a57767dde
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2018-05-09 00:48:05 +00:00
Marshall Dawson
492e4db993 amd/common/pi: Insert missing newline in printk 
Add a newline to the unsupported callout message.

Change-Id: I9bfff0ed920843f6c0818b51ee0046366f2a5c8d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 18:51:22 +00:00
Elyes HAOUAS
d129d43ea7 mb/google: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2018-05-08 18:31:26 +00:00
Elyes HAOUAS
0db963a89e mb/aopen/dxplplusu: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I3857d7ef4eb02974aabe3029abb49efb218cbd93
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 17:52:19 +00:00
Elyes HAOUAS
56f172d9c0 mb/hp: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: Ib9c0d0a85a9e38cdb1bdbcfa055e597f19cf3d5c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 17:51:57 +00:00
Elyes HAOUAS
5bb159a6cf mb/getac: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: Ie5ed621423315388e2b8eb3d5433ef2a7a47d602
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 17:51:00 +00:00
Elyes HAOUAS
6c5925909d mb/biostar: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: Ifc9d82270513f4b4f34d9cf210c37029202b5a5f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 17:50:36 +00:00
Elyes HAOUAS
497737b711 mb/sapphire: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I93b2ce6a26b3a64bd6f4e4c827e9f551b37c6dd0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
 2018-05-08 17:50:02 +00:00
Elyes HAOUAS
092863b460 mb/broadcom: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: Icf7c99ca55d2bcbca2c974d59a63e89758ba5ea6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 17:49:19 +00:00
Duncan Laurie
8735d1bdc7 soc/intel/skylake: Support PCH UART 0 and 1 for console 
The current PCH UART support for console is limited to UART2.

This change adds support for specifying UART0 or UART1 to be
used instead by changing CONFIG_UART_FOR_CONSOLE in the board
level Kconfig.  The default is still 2.

This is tested with a board that uses UART0 for debug output.

Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/26140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-08 14:40:23 +00:00
Paul Menzel
3e582d1613 soc/intel/fsp_broadwell_de: Spell verb *set up* with space 
Change-Id: If2e66f3531696d430b3ae133c4b7ec0d929713b7
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/26129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2018-05-08 14:23:48 +00:00
Elyes HAOUAS
47503cd688 mb/siemens: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: If67ea25a9e1363dde8aefe62b92ee7a61f0458b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
 2018-05-08 14:23:27 +00:00
Elyes HAOUAS
66ea1654f2 mb/sifive: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I8c6358d072b25ab4758637da989883daa600c8ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2018-05-08 14:23:12 +00:00
Elyes HAOUAS
a48390690a mb/winnet: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: Ie6a8364bdd272515e1567061ae0b117392c268aa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2018-05-08 14:22:51 +00:00
Elyes HAOUAS
66e602a7fa mb/supermicro: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: Icc633dc499568cf672f5e244e026e45a6eea5fd8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2018-05-08 14:22:39 +00:00
Elyes HAOUAS
61e07f6ed6 mb/ibase: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: Ief79d8cc1bfdd271e646d09679514560a2c79209
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2018-05-08 14:22:27 +00:00
Elyes HAOUAS
dadfb34c41 mb/iei: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I2e05cfeeae0f1b3a43eab7ee8059dc13cf474022
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2018-05-08 14:22:16 +00:00
Elyes HAOUAS
49c30ba017 mb/iwill: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I39fd521ac2f619ae7b5e12755f09bea5d782eae1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2018-05-08 14:22:05 +00:00
Elyes HAOUAS
4182c80286 mb/intel: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: Ie2c466a280d18979d5f9ca182793ed43431d2010
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2018-05-08 14:18:52 +00:00
Elyes HAOUAS
f5f1b383b1 mb/superio: Rename global control devices as SUPERIO_DEV 
Use SUPERIO_DEV for global control device instead of DUMMY_DEV.

Change-Id: If3555906d359695b2eae51209cd97fbaaace7e61
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25852
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-08 14:18:36 +00:00
Elyes HAOUAS
64b759e201 mb/lenovo: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: Ic044fc074c43db683fcd85ce92a36a8c5a464a67
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2018-05-08 14:17:48 +00:00
Patrick Georgi
a29d234b24 ec/google/chromeec: add config for wake event types 
Avoids array overflow

Change-Id: Ia49a782ba6729c740e3b91c500120132983f6b3c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/25992
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-08 14:16:15 +00:00
Elyes HAOUAS
29c657f4c6 mb/jetway: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I574d9e46ebe6993f356c3617f2e5ff21b5ef55a5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 11:32:07 +00:00
Sathyanarayana Nujella
20c78048a7 mb/google/poppy/variants/atlas: update DMIC NHLT configuration 
From coreboot side, include DMIC 4ch NHLT configuration and its
DMIC blob. In OS side, cras picks the needed channels using UCM's
channel map configuration.
So, this patch updates to include DMIC 4ch config.

BUG=b:79158926
TEST=Verified 4-ch record with arecord
TEST=Also verified internal mic record with cras using
 'cras_test_client --capture_file dmic.raw --rate 48000
	 --num_channels 2 --duration 10'

Change-Id: Ic6df00c2f26ad9cdf54152ab021c2b10499c429c
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-08 03:07:59 +00:00
Julien Viard de Galbert
2d0aaa7fc1 soc/intel/denverton_ns: Fill dimm info for SMBIOS table 17 
Rework display_fsp_smbios_memory_info_hob (shared code).

Import code to convert memory HOB to dimm info for SMBIOS table 17
mostly copied from fsp1_1 mainboard_save_dimm_info.

Change-Id: Id5c4ceaf4e65359f72ec764f0914b5daa82f257e
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23851
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-08 03:06:04 +00:00
Harsha Priya
ad126109ca mb/google/eve: Change rt5663 audio codec's irq as ExclusiveAndWake 
This patch uses GPIO macro to define rt5663 headset codec's irq as
ExclusiveAndWake. This change allows jack detection even when
device is in D3 state.

TEST=Plug in/out jack when the system is in deep sleep and wake up
the system to ensure that jack insertion/removal is detected.

Change-Id: Icb72337025a8408ed7ea9b6e60e938dcb88eae76
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26016
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-08 03:05:02 +00:00
Harsha Priya
a850717dc7 arch/x86/acpi_device: Add macros to define gpio with wake flag 
This patch adds new macros to define gpio with an option to either
enable irq wake (mark it as ExclusiveAndWake flag in SSDT) or disable
it (mark it as just Exclusive flag in SSDT).

Change-Id: Ia71559dcae65112b75e4c789328e4a6153e922b0
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/25838
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-08 03:04:50 +00:00
Elyes HAOUAS
f9de5a4b43 src/southbridge: Add required space before the open parenthesis 
Change-Id: If46db4d210e4b25221436ad1222433d3b00e08e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26035
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-08 03:04:33 +00:00
Elyes HAOUAS
c4c2d4ec7a mb/roda: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I0830e5519256122e3fe9f142c4c8e1e5e85f9a8c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 03:04:17 +00:00
Elyes HAOUAS
f65f297eff mb/kontron: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: Iac341f592acd777fe9ba22cfbca19d4cbdb4916e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 03:03:59 +00:00
Elyes HAOUAS
070b2d97e5 mb/lippert: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I9a51ff76bc4fcd6ca659229c87cd7dd5bf83b43b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 03:03:48 +00:00
Elyes HAOUAS
9adef1ed56 mb/pcengines: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I8a05bb00dc640fafa1c8e2eaac6427fdb0169f39
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 03:03:36 +00:00
Elyes HAOUAS
a2e282b06a mb/apple: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I14d82b0463d184ae89d7137f2dc6732bbb608b73
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 03:03:23 +00:00
Elyes HAOUAS
9981177cb8 mb/gigabyte: Get rid of device_t 
Use of device_t has been abandoned in ramstage.

Change-Id: I37ba054022241c93c03e6c804e46f4e8a1c1143e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-05-08 03:03:11 +00:00
Nico Huber
715a502c17 console: Reduce default loglevel to DEBUG 
The former default SPEW is very noisy, intentionally. It is usually
only useful to debug specific issues and doesn't carry much infor-
mational value.

Reducing the loglevel should also mitigate overflows in pre-CBMEM
console buffers.

Change-Id: Iebcd4681572c58f1d17085c5ef01a2dd49e981ca
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26053
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-08 03:02:25 +00:00
Nico Huber
d4ac11f6fa Move pci_ops_mmconf from arch/x86/ to device/ 
MMConf is not architecture specific. We also always provide a
pci_bus_default_ops() now if MMCONF_SUPPORT is selected.

Change-Id: I3f9b403da29d3fa81914cc1519710ba7d1bf2bb5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26062
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-08 03:01:35 +00:00
Nico Huber
3de303179a {mb,nb,soc}: Remove references to pci_bus_default_ops() 
pci_bus_default_ops() is the default anyway.

Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2018-05-08 03:01:04 +00:00
Nico Huber
ea4d692d57 device/pci_ops: Remove unnecessary weak implementation 
I doubt this is or will ever be referenced anywhere. And if, we
probably shouldn't return.

Change-Id: I3704fec694c5e5a9d5ff7d78d8bf2f23cf463e3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2018-05-08 03:00:48 +00:00
Youness Alaoui
42ff2c05d9 purism/librem13v1: Fix space->tabs and disable ME pci device 
Change-Id: I7ffcea7bff988d3d4269e1334fc938932aed2eb4
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2018-05-08 03:00:15 +00:00
Youness Alaoui
ab0fdcd73d purism/librem13v1: Disable PCI Express AER capability 
The Librem 13v1 does not seem to have working AER and this option
was needed and tested on the Librem 13v1. Without it, the linux
console gets spammed with AER errrors.

Change-Id: I13d0afa085b426920d7a946e6209f924ce29ae52
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2018-05-08 02:59:44 +00:00
Youness Alaoui
7161678407 intel/broadwell: Add option to enable/disable the PCIe AER capability 
The Advanced Error Reporting capability was hardcoded in the PCIe
extended capability list, but it might not always be possible.

The Librem 13v1 does not seem to have working AER and this option
was needed and tested on the Librem 13v1. Without it, the linux
console gets spammed with AER errrors.

Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2018-05-08 02:59:23 +00:00
Youness Alaoui
1f64b01bbe intel/broadwell: If L1 Sub state is disabled, do not set capability 
I finally found out why disabling the L1 sub state option did not
prevent some NVMe drives from locking up in L1 substate. I expect
that the disabled L1 substate initialization that coreboot does
is negated because Linux might itself configure it if it finds the
capability enabled on the PCIe root port.

Removing the capability from the PCIe root port when L1 sub states
are disabled in the configuration should fix the problem.

This was not tested because it's a difficult issue to reproduce and
I do not have the problematic hardware that caused it anymore.

Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2018-05-08 02:58:56 +00:00