Since linux commit f9ba70535dc12d9eb57d466a2ecd749e16eca866
"[PATCH] Increase number of e820 entries hard limit from 32 to 128"
made in 2005 the number of e820 entries passed from the bootloader
is 128. Use the boot protocol version to check for support of
128 entries and use them if necessary.
Tested on IBM/SBP1:
Fixes booting a Linux payload when more than 32 entries are present
in the memory table, which can easily happen on a 4 socket platform.
Change-Id: Iec0a832fff091b6c3ae7050ef63e743a30618f25
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Now that the baseboard uses chipset devicetree references, remove
all references whose value is identical to the chipset devicetree
default or the baseboard default, since they are pointless clutter.
TEST=build/boot purism/librem_cnl (Mini v2), verify output of lspci
and lsusb unchanged before and after patch.
Change-Id: I12498e7261dafd7ee59fe79926532399392d1b09
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80600
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the board uses chipset devicetree references, remove all
references whose value is identical to the chipset devicetree default,
since they are pointless clutter.
TEST=build/boot purism/librem_cnl (Mini v2), run lspci and verify output
unchanged before and after patch.
Change-Id: I6c656d227962548cebde61f1d82333837adbbf56
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80599
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch eliminates coreboot from loading microcode from RW CBFS
(when the RO descriptor is locked, which indicates a fixed RO image)
because the kernel can already patch the microcode on BSPs and APs
while booting to OS.
This may be a chance to lower the burden on the AP FW side because
patching microcode on in-field devices is subject to firmware updates,
which are rarely published and, if required, must go through the
firmware qualification testing procedure (which is costly, unlike
kernel updates for ucode updates).
1. The FIT loads the necessary microcode from the RO during reset.
2. Reloading microcode from RW CBFS impacts boot time
(~60ms, core-dependent).
3. The kernel can still load microcode updates.
ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is
sufficient for initial boot, and the kernel can apply updates later.
BUG=none
TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode
loading when RO is locked.
Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Select this at the SoC level (like other modern Intel SoCs), and drop
it from individual boards which selected it.
Change-Id: I8ebb915fbc21f82e39304473b0fcaa620559b5d5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80558
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's already selected at the SoC level, so selecting at the board
level is redundant.
Change-Id: Ifbe7f88858b9e5e8e5185dbff5853186fd3c66cb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80557
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add an ACPI stub containing the TCPU device in proper scope, along with
the device status, on boards not using the DPTF driver, so that there
exists an ACPI device to be referenced from the PEPD LPI constraint
list.
Adding the stub fixes an AE_NOT_FOUND ACPI error under Linux for
_SB.PCI0.TCPU on boards with the SA thermal device enabled but which do
not use the Intel DPTF driver.
TEST=build/boot Linux,Win11 on purism/librem_cnl (Librem Mini v2).
Change-Id: I926d0461e5e0dfaf606102575c2be555a6bfb695
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is now generated by acpigen in the common/block/sata module.
Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
acpi_device_path() includes the device name, so we end up with:
Scope (\_SB.PCI0.SATA) {
Device (SATA) {
...
Fix this by using acpi_device_scope() instead.
TEST=build/boot purism librem_cml (Mini v2), dump ACPI and verify
SATA device scope correct.
Change-Id: Ibbc8890d93b22f0ecba4b3a9b0531994574b3d55
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80554
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This is used in util/cbfstool/elf.h and lzmadecode.
Change-Id: I75e71259f23bee602ffb54b0c51e0e4a9da3f8e5
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
These strings didn't match the license names exactly, so update them
to match.
Change-Id: Ib946eb15ca5fa64cbd6b657350b989b4a4c1b7b7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: I81dd67fd200768942fe355180b75db0746cda8ea
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
When 'reset_gpio' and 'enable_gpio' properties are defined in
overridetree.cb, the kernel will power on the FPMCU. If the device was
previously enabled the kernel will reset it.
To avoid situation in which the FPMCU is powered on and reset later we
leave the FPMCU powered off in coreboot and started by the kernel. This
is exactly what other boards do (e.g. brya).
TEST=Boot the board (e.g. karis) and make sure the FPMCU was booted once
(e.g. examine FPMCU console logs)
Change-Id: I5df8d9385be2621c02ccee2d36511a4e80ab87d1
Signed-off-by: Patryk Duda <patrykd@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80457
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting the EC interrupt GPIO as an APIC is able to solve many
problems that we are currently seeing:
1. Routing through the APIC make the IRQ# associated with this pin
unavailable to claim for other devices in the kernel. This is causing
EC interrupts to not work.
2. Since EC interrupt are not working, we are not able to flash the
EC from the DUT.
3. Also, the GPI_INT configuration does not allow us to set the
polarity of the GPIO, which means that it is by default set as active
high. As a result, we are seeing an excessive number of host command
interrupts to the EC. This disappears when we change the
configuration to APIC and set the polarity as INVERT.
BUG=b:319129926,b:324707182
BRANCH=None
TEST=1. After boot up, check if ec_cros_lpcs driver was successfully
registered. Look for the following string:
"cros_ec_lpcs GOOG0004:00: Chrome EC device registered"
2. Make sure can flash the EC image from the DUT
3. Make sure EC console is not getting continuous stream of host
commands.
Change-Id: I74bff88d2ddbaf1f4b085c31d582bd66e18c438a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80467
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.corp-partner.google.com>
This patch increases the IgdDvmt50PreAlloc value as per Intel
recommendation starting with GFX PEIM 103x.
TEST=Able to build and boot google/rex.
Change-Id: I236b38a1ac5efbfcd23e373c09204d8a07b97618
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80406
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Rename tcss_mux_init to disconnect_tcss_devices to make it clear
what this function is doing, as it doesn't initialise anything.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5e43f0cca9d49bc30fc189663490a306efd71584
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79874
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Configure PMC mux in devicetree. This allows PD controllers to be
used for both video and power delivery.
Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD
display can supply power and display video output.
Change-Id: I580b148b036e62fbcab50d1ca2ab1ed021cfed6b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure PMC mux in devicetree. This allows PD controllers to be
used for both video and power delivery.
Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD
display can supply power and display video output.
Change-Id: I9e49612d7f165a9c9604093535f7b141a4c7048c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79426
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the ubtc.asl as it's no longer needed.
Change-Id: I8564bb7d9bd94c8303c543c078bc76192539c5f2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80484
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These entries no longer exist as they are stored in CFR.
Change-Id: Ia85855fddc36db76a65490a1d685e1943db28b74
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 977b8e83cb0a ("mb/emulation/qemu-aarch64: Add MMU support") adds
MMU support for ARM64 QEMU VMs, but registers a limited 1GiB region for
the DRAM, with a note that ramstage should update it.
However on recent versions of QEMU "virt" VMs, accessing RAM outside
this registered region results in an exception even if the address is
backed by actual RAM. This interferes with RAM detection which catches
these exceptions, effectively limiting us to detecting a maximum 1GiB of
RAM even if more is available.
Register the entire RAM space to MMU instead of just the 1GiB, so that
probing RAM addresses can correctly detect how much RAM we have.
Change-Id: I3afbd27b91ab37304a29a62506f965ac3cfb1c06
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This port is not connected on the X230, X230i, X230t.
When X230 support was introduced and pei_data was filled in, this port
was disabled, but after commit 3dc12c1e1918
(bd82x6x: Consolidate early native USB init) it has become enabled.
Change-Id: I952193798c0894b256b21d9fb3f238074ff5f0f0
Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80468
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The unused soft_reserved_ram_resource expanded to the non-existent
fixed_mem_resource function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b454175c6530e539aa24dffb771368b0aea6da9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This tool doesn't have a makefile, when trying to compile it manually
with the given instructions it even fails to compile after fixing the
paths in the given command, and it references the non-existing
PCI_BUS_SEGN_BITS Kconfig symbol, so just drop this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8ca75db281a215bf3f194ab72a107f666dc0694e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79934
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Normally this would be done by the Intel GMA driver, but we can't have
two copies of the _DOD method, so generate the LCD backlight controls
here to allow use of this driver instead of the default GMA panel
definition.
TEST=build/boot Win11 on google/byra (redrix), ensure ACPI brightness
controls functional.
Change-Id: Ic8fbaf7550405f8c6f36012c8efadb8c36b968c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80061
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TCC offset is configured in devtree.c, so remove it from
the devicetree.
Change-Id: I044a68854cc142b057cf31b4e2456d2ad1d0dd3a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As DRIVERS_PS2_KEYBOARD isn't set, this function is not doing anything.
Change-Id: Ie8842a32fca56f330a0f044cf96112dc5cae6546
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
There is a modification for the x230 which uses the 2nd DP from the
dock as the integrated panel's connection, which allows using a custom
eDP panel instead of the stock LVDS display.
There are several adapter boards present on the market and all of them
use the same method of enabling the custom eDP panel.
To make this work with coreboot, the internal LVDS connector should be
disabled in libgfxinit. Additionally, VBT has been modified to keep
brightness controls functional on the adapter boards that use LVDS for
the job.
The modifications done to the VBT are:
- Remove the LVDS port entry.
- Move the DP-3 (which is the 2nd DP on the dock) entry to the first
position on the list.
- Set the DP-3 as internally connected.
This has been reported to work with the following panels:
- LP125WF2-SPB4 (1920*1080, 12.5")
- LQ125T1JW02 (2560*1440, 12.5")
- LQ133M1JW21 (1920*1080, 13.3")
- LTN133HL10-201 (1920*1080, 13.3")
- B133HAN04.6 (1920*1080, 13.3")
- B133QAN02.0 (2560*1600, 13.3")
Other eDP panels not on this list should work as well.
Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
