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16 Commits

Author SHA1 Message Date
Subrata Banik
7e8998466f soc/intel/common/block: Move cse common functions into block/cse 
This patch cleans soc/intel/{cnl, icl, tgl} by moving common
soc code into common/block/cse.

Supported SoC can select existing HECI_DISABLE_USING_SMM option to
select common cse code block to make heci function disable using
sideband interface during SMM mode at preboot envionment.

BUG=b:78109109
TEST=Able to make HECI disable in SMM mode successfully without any hang
or errors in CNL, ICL and TGL platform.

Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-02-25 10:13:08 +00:00
Subrata Banik
00b7533629 soc/intel/common/block: Move smihandler common functions into common code 
This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc
code into common/block/smihandler.c

BUG=b:78109109
TEST=Build and boot KBL/CNL/APL/ICL/TGL platform.

Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-02-25 10:12:19 +00:00
Kyösti Mälkki
d5f645c6cd soc/intel: Replace config_of_path() with config_of_soc() 
The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.

Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.

Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-10-02 11:21:10 +00:00
Kyösti Mälkki
8950cfb66f soc/intel: Use config_of() 
Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
 2019-07-18 15:25:35 +00:00
Kyösti Mälkki
903b40a8a4 soc/intel: Replace uses of dev_find_slot() 
To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.

Replace this with method that relies on bus topology
that walks the root bus only.

Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-07-04 09:48:22 +00:00
Subrata Banik
a0368a0950 soc/intel/{cml, whl}: Add option to skip HECI disable in SMM 
This patch provides an additional option to skip HECI function
disabling using SMM mode for WHL and CML platform, where FSP has
dedicated UPD to make HECI function disable.

User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated
UPD.

Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig
to make HECI disable and WHL/CML has to rely on FSP to make HECI
disable.

Change-Id: If3b064f3c32877235916f966a01beb525156d188
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-06-13 04:38:39 +00:00
Elyes HAOUAS
c3385070d6 soc/{amd,intel}/chip: Use local include for chip.h 
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-04-26 16:49:13 +00:00
Julius Werner
cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 
This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2019-03-08 08:33:24 +00:00
Subrata Banik
7837c203d6 soc/intel/common/block: Move p2sb common functions into block/p2sb 
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/p2sb.

BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.

Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2018-06-28 08:35:29 +00:00
Elyes HAOUAS
c8a649c08f src: Use of device_t is deprecated 
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2018-06-14 09:29:31 +00:00
Subrata Banik
e83d057c3e soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode 
TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree.

Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-02-22 09:56:37 +00:00
Subrata Banik
261b893b7c soc/intel/{apollolake, cannonlake, common, skylake}: Add _soc_ prefix in weak function 
This patch ensures all soc function name is having _soc_ prefix
in it.

TEST=Able to compile SMM common code for all supported SOC.

Change-Id: Iab1b2f51eaad87906e35dbb9e90272590974e145
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-12-23 05:23:09 +00:00
Subrata Banik
1a274f406c soc/intel/cannonlake: Add SoC API to make use SMM common code 
Add SoC API to detect any illegal access to write into the
BIOS located in the FWH.

Change-Id: If526cbae9afee47fa272bdf74e04416aff100e88
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2017-12-22 01:44:02 +00:00
Subrata Banik
47a655cde3 soc/intel/common: Add missing SoC common function into SMM library 
Modify SMM common code in order to accommodate SKL, CNL, APL, GLK
SOC code.

Change-Id: Ie9f90df3336c1278b73284815b5197400512c1d2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22869
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-12-22 01:41:30 +00:00
Lijian Zhao
f0eb99996d soc/intel/cannonlake: Fill the SMI usage 
Add SMM support for Cannonlake on top of common SMM, also include the
SMM relocate support.

Change-Id: I9aab141c528709b30804d327804c4031c59fcfff
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-10-03 20:23:41 +00:00
Brandon Breitenstein
ae1548621a soc/cannonlake: Enable SMM code for Cannon Lake 
The minimum needed defines are included here and pm.h
will be updated when the PMC code for cannonlake is uploaded.

Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20849
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-11 16:04:42 +00:00