7e8998466f
This patch cleans soc/intel/{cnl, icl, tgl} by moving common
soc code into common/block/cse.
Supported SoC can select existing HECI_DISABLE_USING_SMM option to
select common cse code block to make heci function disable using
sideband interface during SMM mode at preboot envionment.
BUG=b:78109109
TEST=Able to make HECI disable in SMM mode successfully without any hang
or errors in CNL, ICL and TGL platform.
Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017-2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/smihandler.h>
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#include <soc/soc_chip.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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/*
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* Specific SOC SMI handler during ramstage finalize phase
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*
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* BIOS can't make CSME function disable as is due to POSTBOOT_SAI
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* restriction in place from CNP chipset. Hence create SMI Handler to
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* perform CSME function disabling logic during SMM mode.
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*/
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void smihandler_soc_at_finalize(void)
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{
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const struct soc_intel_cannonlake_config *config;
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config = config_of_soc();
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if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
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heci_disable();
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}
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const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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[PM1_STS_BIT] = smihandler_southbridge_pm1,
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[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
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[GPIO_STS_BIT] = smihandler_southbridge_gpi,
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[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
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[MCSMI_STS_BIT] = smihandler_southbridge_mc,
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[TCO_STS_BIT] = smihandler_southbridge_tco,
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[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
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[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
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};
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