From `Documentation/coding_style.md`:
> This does not apply if only one branch of a conditional statement is a
> single statement; in the latter case use braces in both branches:
Change-Id: I5672949e587a9c0e4efa01521a659e4c224085d0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Some of the revision 4 FADT fields were already updated to ACPI
spec revision 6, but not all of them. In addition the advertised
FADT revision was 3.
Implement all fields as defined in version 6 and bump the advertised
FADT revision to 6.
Also set all used access_size fields and x_gpe0_blk to sane values
as Windows 10 verifies those fields starting with FADT revision 5.
Fixes: https://ticket.coreboot.org/issues/109
Tested on Windows 10.
Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is
set because PM timer emulation is enabled via MSR 121h so the timer will
still work and can be used by things like Tianocore and Windows.
Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT).
Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.
Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.
Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.
Replace this with method that relies on bus topology
that walks the root bus only.
Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enable VT-d through fsp upd VtdDisable. Update remapping structure
types in numerical order as all remapping structures of type 0 (DRHD)
enumerated before remapping structures of type 1 (RMRR), and so forth.
BUG=b:130351429
TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Since ACPI v2.c, this field is access_size.
Currently, coreboot is using ACPI v3,so we can drop '.resv' field.
Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to
implement GPIO toggling method, covered for both CNP_LP and CNP_H pch.
BUG=N/A
TEST=Build and boot up fine on sarien platform, add an dummy STSX in
DSDT table, read back from iotools to confirm the GPIO tx state get
updated.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f
Reviewed-on: https://review.coreboot.org/c/30461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The function to fill out the FADT table exits early if the devicetree
config option to disable the legacy timer is set. This means it never
gets to the later check for s0ix config option and so the flag to
indicate that it supports low-power idle in S0 is not set.
Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28755
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0
if S0ix is enabled for the platform. This also sets the
FSPUPD to indicate the status of S0ix on the platform.
TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag
is set in FACP table - FADT.Flags[21] bit.
Change-Id: I6214ebb61f25ef8b704e60c8474808493c92e6f6
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25292
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Basic ACPI support for CNL on top of common ACPI, which will establish
a root of FADT table, fill MADT entry, create gnvs field, record wake
status and convert device names into DSDT dev definitions.
Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
