Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config
option. Select CAR_HAS_SF_MASKS for Tigerlake.
During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x
are not being reset to default as
per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5.
Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient.
Bug=b:171601324
BRANCH=volteer
Test=Build and boot to ChromeOS on Delbin.
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SF Mask MSRs' Programming which was done under this config
selection will be moved under a new config option called
CAR_HAS_SF_MASKS. This segregates the eNEM programming
sequence based on sub features supported in each processor.
Bug=b:171601324
BRANCH=volteer
Test=Build volteer build and boot on Delbin EVT.
Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is not meant for actual use, but to build-test several options.
Please do not try to use it on real hardware. Or maybe do try.
The purpose of this config is to build-test the individual options, not
their combination. So, for instance, if it would be hard to keep options
x, y and z build together in the future, this config shouldn't block a
change but should instead be adapted, e.g. split into multiple chunks.
Change-Id: I80e8fe3982025b61148e7c2b05dd0727d65ee2f4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The patch sets up the CSE Lite driver in the romstage instead of ramstage.
With this change, CSE Lite driver sets CSE's boot partition and triggers
CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM
initialization as HMRFPO_ENABLE HECI command (which is used by
cse_fw_sync()) is expected to be executed after DRAM initialization. With
this change, it improves the cold boot time by ~154ms.
Test=Verified on JSL and TGL platforms
BUG=b:174694480
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch modifies CSE Lite driver to use 'if' C-lanugage construct
instead of #if macro and adds 'if SOC_INTEL_CSE_RW_UPDATE' to the prompts
of CSE Update related KConfigs to prevent appearing them in the menu.
TEST=Built the code for drawcia
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Iecd5cf56ecd280de920f479e174762fe6b4164b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This seems to be a debugging option. Since unset devicetree options
default to zero, drop the setting. If it is needed in the future, a
user-visible Kconfig option would probably make more sense.
Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The upcoming Librem 14 variant won't use the same SATA HSIO adjustments
as the Librem Mini, so move these settings into a variant-specific file.
Rename existing gpio.h to variant.h, move to board root directory, and
use for all variant-specific declarations; adjust references as needed.
Add newly-created variant.c to Makefile.
Test: build/boot Librem Mini, verify SATA functionality unchanged.
Change-Id: Ie8f714cc759675c692ad6e3f20e50adad8d09d4b
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48519
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, the option to cache DIMM SPD data in an FMAP region
is closely coupled to a single board (google/hatch) and requires
a custom FMAP to utilize.
Loosen this coupling by introducing a Kconfig option which adds
a correctly sized and aligned RW_SPD_CACHE region to the default FMAP.
Add a Kconfig option for the region name, replacing the existing hard-
coded instance in spd_cache.h. Change the inclusion of spd_cache.c to
use this new Kconfig, rather than the board-specific one currently used.
Lastly, have google/hatch select the new Kconfig when appropriate to
ensure no change in current functionality.
Test: build/boot WYVERN google/hatch variant with default FMAP, verify
FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log.
Also tested on an out-of-tree Purism board.
Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently it's not possible to add multiple graphics drivers into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics drivers can use.
This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel+Aspeed on server platforms or
Intel+Nvidia on consumer notebooks.
The goal is to remove duplicated fill_fb_framebuffer(), the advertisment
of multiple independent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.
Replace all duplications of fill_fb_framebuffer and provide a single one
in edid_fill_fb.c. Should not change the current behaviour as still only
one graphic driver can be active at time.
Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do not mislead newcomers into thinking the GM45 series laptops are hard
to flash. Describe the simple coreboot flashing procedure first, then
explain how to remove the ME firmware and use a custom flash layout.
Also, reword a sentence on the simple flashing procedure for clarity.
Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
For EHL, SpiProtectionMode is added to HFSTS register #1.
The original Manufacturing Mode is detected via FpfSocConfigLock
instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode,
and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48539
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mt8183 dsi driver can be shared with mt819x SoC.
Move dsi.c to common/ folder and rename it to dis_v2.c to
differentiate it from mt8173's dsi driver.
TEST=emerge-kukuki coreboot
Change-Id: I722d3e67f230ab8eb729900cdf15b922eb91a072
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Add I2C controller for MT8192, and revise the common I2C driver
to support I2C controller running in APDMA async mode. In that
case we have to initiate a different handshake protocol and reset
I2C differently.
BUG=b:155715435
TEST=Asurada boots up to shell
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
SMIs and SCIs aren't used before ramstage or the OS, so there should be
no need to already set them up in romstage. Not using this GPIO
configuration functionality allows untangling the GPIO and smi_util code
and only linking smi_util in ramstage in follow-up patches. In romstage
the pins get initialized as inputs with pull-up, so that at least that
part still matches the configuration before this patch.
BUG=b:175386410
Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
