This patch performs below operations to enable LAN0.
- Complete the LAN PEREST power sequencing
- Program the SRC_CLKREQ (GPP_D20) with correctly.
- Add overridetree.cb entry to configure the LAN0 device.
BUG=b:289395519
TEST=Able to boot google/ovis with LAN0 being enabled.
Change-Id: I91b0a76395ade4459cf8705c333728a71f95df14
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76213
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch performs below operations to enable LAN1.
- Add overridetree.cb entry to configure the LAN device.
- Complete the LAN1/SD PEREST power sequencing
BUG=b:289395519
TEST=Able to boot google/ovis with LAN1 being enabled.
Change-Id: Ifb67cb8e6fc03e3ff14b1b3d8382322fd0b3aeff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76212
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures GPP_V12 aka SOC_SLP_LAN_L properly as per the
Ovis schematics dated June'23 to ensure LAN port is not in sleep.
BUG=b:289395519
TEST=Able to measure SLP_LAN PIN and confirm it's deasserted.
Change-Id: I1fe8715862823149c8a1f05e3e4463a615fbbbce
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76211
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures GPP_C10 aka EN_LAN_RAILS properly as per the Ovis
schematics dated June'23 to ensure LAN ports having power.
BUG=b:289395519
TEST=Able to measure LAN port power is enabled with this CL.
Change-Id: I3f4d611313325dba66905e0c8ef391765a1fe7a7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
flashrom does not support libftdi 0.20 anymore and it's not used by
anything else. Its build systems (Makefile and Meson) only reference
libftdi1 and it still compiles fine without the legacy package. Thus,
drop it from the package list.
Change-Id: If1b575bc9abfd192e93811a83d8615bed61eba0c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
flashrom does not support libusb 0.1 anymore and it's not used by
anything else. Its build systems (Makefile and Meson) only reference
libusb1 and it still compiles fine without the legacy package. Thus,
drop it from the package list.
Change-Id: Ib9b7530e5b707e12fbf3f8058999456dc1f8dff4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This was missed recently when adding the table. Linux complains about
the missing checksum, e.g.
[ 0.186070] ACPI BIOS Warning (bug): Incorrect checksum in table [SPCR] - 0x00, should be 0x87 (20210730/tbprint-173)
Tested with QEMU/Q35, albeit with changes to the special handling for
ACPI with QEMU. The warning goes away.
Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 90464073e4 (acpi: Add SPCR table)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76158
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In mtl, there is no MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE
So, this patch removes unused code related to
MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE
ADL also removes this code, see cl:62861
BUG=b:288976547
TEST=Tested on Screebo and DP/USB are working as expected after suspend/resume
Change-Id: I5a4b26c38ec3f5fe1d81fd70f8c2196d0e5b84c3
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76126
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SOC/IOE SRAM device is used to store crash logs. Previously, the
crashlog enablement was hardcoded in the baseboard.common module.
This commit moves the crashlog enablement logic to the baseboard
module, so that it can be enabled or disabled based on the specific
baseboard.
Additionally, the SOC/IOE SRAM is now enabled by default in the
baseboard devicetree.cb file. This prevents the system from hanging
if the SOC/IOE SRAM device is not present.
BUG=b:262501347
TEST=Able to build and boot google/screebo with this patch.
w/o this patch:
[ERROR] SOC SRAM device not found!
[ERROR] IOE SRAM base not valid
Change-Id: I02d581e5b62cfa114a3761a9704ad9f24dead8aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When probing the resource with the IOMMU_IOAPIC_IDX index, we need to
use the PCI device 0 function 0 on the first bus in the domain for
probing and not the domain device, since the resource isn't on the
domain device, but on the northbridge device which is B0F0D0 in the case
of the APUs.
TEST=This fixes the following error on Mandolin with Picasso:
AMD-Vi: [Firmware Bug]: : IOAPIC[1] not in IVRS table
AMD-Vi: Disabling interrupt remapping
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id88f17d68ba5accef6561837478828bd3d24baa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76117
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Hades uses DDR5 which can't read SPD from coreboot yet. Use smbios
dump to print memory information.
TEST=check the coreboot log.
memory Channel-0-DIMM-0 type is DDR5
memory part number is MTC8C1084S1SC56BG1
memory max speed is 5600 MT/s
memory speed is 5200 MT/s
memory size is 16384 MiB
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ica44081228a3a1edc36e2110e84686582fbe8f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This patch avoids random hang issue observed after booted to OS on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s.
As per Intel doc 769410 the expected work around is to change SAGV
point 0 from 2133 G4 to 3200 G4.
BUG=b:287170545
TEST=Able to perform 500 power cycles on google/rex without any hang.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I02a9cadc075f396549703d7a008382e76268f865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76076
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Assign the current address casted to acpi_ivrs_ivhd[11,40]_t pointer to
*ivhd_[11,40] at the beginning of acpi_fill_ivrs[11,40] and then use
memset on *ivhd_[11,40] to zero-initialize the structs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I70b12fee99d6c71318189ac35e615589a4c8c629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76077
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
