To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.
Replace this with method that relies on bus topology
that walks the root bus only.
Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Clang Static Analyzer found version 8.0.0 gnvs is allocated, but
it is never used. Change sizeof(*gnvs) to sizeof(global_nvs_t)
while adding ACPI GNVS to CBMEM.
TEST=Built and boot up to kernel.
Change-Id: Ie9421af4a556d1d88183aa938ee2a124a10ab727
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reset GPI Interrupt status and enable registers from ramstage instead of
bootblock so that it applies to devices in field.
BUG=b:130593883
BRANCH=octopus
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.
Change-Id: Ib11b580ceb23bd1fe789f549b667a8ced2d859a1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32534
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A hook for romstage is already existing but not for ramstage.
It's very useful for debugging as it allows to run code
for testing purposes by the mainboard. Also, it allows to
run configuration code or configure FSP options, which
don't have a devicetree option.
Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The FSP has a parameter to enable or disable the VTD feature
(Intel's Virtualization Technology for Directed I/O). In current header
files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to
disabled per default. Therefore, if the FSP was not modified via BCT,
this feature is most likely disabled on all mainboards.
Add a chip parameter so that VTD can be enabled on mainboard level in
devicetree and therefore this feature can be activated if needed.
Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31194
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GLK has a dedicated USB2 port that is used specifically for CNVi
BT. This requires that the ACPI tables define an additional USB 2 port
which results in _ADR for USB 3 ports being different for GLK than
APL.
This change splits the ports in xhci.asl into APL and GLK specific
ports.asl and selects the appropriate file based on
CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK
if ACPI name is requested for that port.
BUG=b:123670712
BRANCH=octopus
TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and
for reef (APL) does not include HS09 definition.
Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31172
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SoC has an Image Processing Unit which is located on PCI 00:03.0.
There is a corresponding parameter for FSP which handles
enabling/disabling of this functionality (IpuEn). Add this device to
the disable_dev() function of the chip so that if this device is
disabled in devicetree the matching FSP parameter will be disabled as
well. As this parameter is only valid for Apollo Lake, use the config
switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for
Apollo Lake. As this issue is regarding a missing structure member,
this check needs to be done on preprocessor level and not at runtime.
Test=Verified this function on mc_apl2.
Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It was observed system suspend/resume failure while running
RunInDozingStress. Apply correct GLK usb clock gating register
value to mitigate the failure.
BRANCH=octopus
BUG=b:120526309
TEST=Verified GLK clock gating register value after booting
to kernel.
Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Provide options to disable xHCI Link Compliance Mode. Default is FALSE
to not disable Compliance Mode. Set TRUE to disable Compliance Mode.
BRANCH=octopus
BUG=b:115699781
TEST=Verified booting to kernel.
Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30816
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sync the FSP settings with what coreboot does. Why both FSP and coreboot
configure this redundantly stays a secret.
TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC
works correctly now, but was confused by the wrong settings before
because the FSP defaults allowed to disable the LPC clock.
Change-Id: Id1c7180f460678bf0f9458228591050dd628c052
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This change disables HECI1 device at the end of boot sequence. It uses
the P2SB messaging to disable HECI1 device before hiding P2SB and
dropping privilege level.
BUG=b:119074978
BRANCH=None
TEST=Verified that HECI1 device is not visible in lspci on octopus.
Change-Id: Id6abfd0c71a466d0cf8f19ae9b91f1d3446e3d09
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures
USB-C as device mode. Force USB-C into host mode.
BUG=b:111623911
TEST=Verified that USB-C being host mode once USB OTG is set.
Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SoC users from IOTG team is looking forward for a solution to skip
coreboot AP initialization flow and make use of FSPS-UPD to
perform AP reset.
TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs
out of reset.
Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for APL and GLK.
Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With
PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table
entry for this range which caused a page fault. Since this test
is anyway not exhaustive, we will skip the memory test in FSP.
There is an option to do PCIe power sequence from within FSP if provided
with the GPIOs used for PERST to FSP. Since we do this from coreboot,
will skip the PCIe power sequence done by FSP.
FSP does not know what the clock requirements are for the device on
SPI bus, hence it should not modify what coreboot has set up. Hence
skipping SPI clock programming in FSP.
CQ-DEPEND=CL:*627827
BUG=b:78599939, b:78599576, b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26284
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for
any root hubs that may be present.
Recent Intel platforms route all ports to an XHCI controller
through a root hub. This is supported by considering the root
hub to be USB port type 0, the USB 2.0 ports to be type 2, and
the USB 3.0 ports to be type 3.
This was tested with a Kaby Lake platform by adding entries to
the devicetree and checking the resulting SSDT.
Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
MONITOR/MWAIT had an irremediable hardware bug for Apollolake.
This has been fixed for GLK. Therefore, make MONITOR/MWAIT based
C-states the default for GLK and disable IO-Redirection based
C-states used for Apollolake.
Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state
residencies with and without load.
Tested for S0ix entry and exit using:
"echo freeze > /sys/power/state" and "suspend_stress_test -c 500".
BUG=b:77639897
Change-Id: If648c25a9b26c04b278dce4af241d439790288ca
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/19718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
Change-Id: I5aea15511c52d1191babf551feb237f4144683e4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PCIe de-emphasis is enabled by default. Thunderpeak Wi-Fi requires
it to be disabled. Therefore allow it to be configured via a
device tree setting.
TEST=On GLKRVP, verify Thunderpeak Wi-Fi card shows up in lspci when
de-emphasis is disabled in device tree.
Change-Id: Iae204768dfe00a638c764644c44c7cda269e73e0
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpHotPlug in apollolake UPD is default enabled. This change adds a
config option to enable hotplug only if explicitly requested by
mainboard. This changes the default behavior on all apollolake boards
to have hotplug disabled.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Intel common PCI driver is handle PCI subsystem ID
programming, hence no need to have an explicit soc
function to do the same.
TEST=PCI subsystem id is getting programming during
pci enumeration.
Change-Id: I3eb362ff1f3f6d5c81a0dbe854d8ecd59d5a0453
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Using common p2sb driver instead of private one.
TEST=Boot up into OS, and read back registers through PCR by iotools,
return is not 0xffffffff.
Change-Id: I30f3ef7bc37a8cb268af6fe2e4da3ec835c17633
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of having all callers provide a region_device just for the
purpose of reading vbt.bin, let locate_vbt handle its entire life cycle,
simplifying the VBT access API.
Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The System Control Interrupt is routed per default to IRQ 9. Some
mainboards use IRQ 9 for different purpose. Therefore it is necessary to
make the SCI configurable on Apollo Lake.
Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
