The MAX98363 smart speaker amp can be connected over SoundWire and be
configured for mainboards to use:
- Data Port 0 and Bulk Register Access is not supported
- Data Port 1 is the 32bit data input for the speaker path
The data port and audio mode properties are filled out as best as
possible with the datasheet as a reference.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
For example this device is connected to master link ID 2 and has strap
settings configuring it for unique ID 0.
chip drivers/soundwire/max98363
register "desc" = ""Left Speaker Amp""
device generic 2.0 on end
end
This driver was tested with the rex0 reference design by booting
and disassembling the runtime SSDT to ensure that the devices have the
expected address and properties.
Device (SW20)
{
Name (_ADR, 0x000230019F836300) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_DSD, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-sw-interface-revision", 0x00010000 },
[...]
Package () { "mipi-sdw-source-port-list", Zero },
Package () { "mipi-sdw-sink-port-list", 0x02 }
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" },
Package () { "mipi-sdw-dp-1-sink-subproperties", "SNK1" }
}
})
Name (MOD0, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-audio-mode-bus-frequency-configs",
Package () { 0x00927C00, ... }
},
Package () { "mipi-sdw-audio-mode-sampling-frequency-configs",
Package () { 0x3E80, ... }
},
[...]
}
})
Name (SNK1, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-data-port-type", Zero },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }
}
})
}
BUG=b:269497731
TEST=Verified SSDT for SNDW in the OS
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ie56109d615759e3e5e32782c8782cb2f47014ec4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73278
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even though coreboot does not allow floating point operations some
compilers like clang generate code using hw floating point registers,
e.g. SSE %XMMx registers on 64bit code by default. Floating point
operations need to be enabled in hardware for this to work (CR4). Also
in SMM we explicitly need to save and restore floating point registers
for this reason. If we instruct the compiler to not generate code with
FPU ops, this simplifies our code as we can skip that step.
With clang this reduces the binary size a bit. For instance ramstage for
qemu/Q35 drops from 216600 bytes decompressed to 212768.
TEST: See that with x86_64 bit and clang coreboot reaches the payload
without setting the CR4_OSFXSR bit in CR4. Without this change it would
bootloop very early in the bootblock on Qemu Q35.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib8590c55e7aed1ece2aa23b8ea99463396435e11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75316
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit f99d6700 ("mb/google/skyrim/var/winterhold: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot winterhold, dump ACPI, verify unchanged
Change-Id: Ia9982fed0fe2093d787ee9506ac5bbadd6cc03f9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75389
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Commit d81ee3f1 ("mb/google/skyrim/var/markarth: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot markarth, dump ACPI, verify unchanged
Change-Id: I5c1cd23c49b512f55e9e13b2164d30dfb7fb682d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75388
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Commit a539893c ("mb/google/skyrim/var/frostflow: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot frostflow, dump ACPI, verify unchanged
Change-Id: I3912fe1b7d3f2a07cb379928cd4f5d87100d3284
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75387
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch adds an enum macro to define the different SaGv work points.
The enum macro is named `sagv_wp_bitmap` and it has three values:
The goal is to choose the optimal SaGv work point for the target
platform after considering the two inputs as power consumption and performance. The first group is for workloads that require high performance, even if it means consuming more power. The second group
is for workloads that can tolerate lower performance, in order to save
power.
SAGV_POINTS_0_1: The highest power consumption, but also the highest
performance.
SAGV_POINTS_0_1_2: A lower power consumption than work point
SAGV_POINTS_0_1, but also a lower performance.
SAGV_POINTS_0_1_2_3: The lowest power consumption, but also the lowest
performance.
Set SaGv work points after reviewing the power and performance impact
with SaGv set to 1 (Enabled) and various considering various work points
between 0-3 being enabled.
BUG=b:267879107
TEST=Able to build google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4af0038f2799a458d1b006270068341f65d36609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75362
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be
able to train memory (DIMM) at different frequencies.
On all latest Intel based platforms SaGv is expected to be enabled
to support dynamic switching of memory operating frequency.
BUG=b:267879107
TEST=Able to verify SaGv is enabled with 3 work point (0, 1 and 2)
and MRC retraining takes around ~20ms extra compared to SaGv being
disabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic680bfeab4dd285c0d3916ba5e917cc12bae3284
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73534
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A directory for tarballs is needed in any case but it's created at build
time. However, in reproducible build environments the sources are
downloaded before the buildgcc scripts runs and the directory needs to
be created.
Thus, to simplify that, add an empty tarballs directory.
Change-Id: Id3b4bf918c93f10c145f580684e916a4f8bae3b1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The payload API of coreboot described in
https://www.coreboot.org/Payload_API does not reflect the current
handoff mechanism to hand the coreboot tables off. Therefore the
arguments supplied by coreboot (cbtable) will currently never be parsed
correctly and libpayload has to search for the coreboot tables by
iterating through memory.
This patch removes the old payload API implementation and just takes the
coreboot table pointer from the first argument on the stack.
Tested: started prodrive/atlas with coreinfo payload
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I51fb0cfc81043cbfe3fc9c8ea0776add2d6a42b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74965
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add devicetree and Kconfig entries to enable additional configuration
of the Pericom PI7C9X2G608GP PCIe switch on this board variant.
The amplitude is being adjusted to 425 mV and de-emphasis level to
6.0 mV.
BUG=none
TEST=Read out the PCIe config space values of the switch and check if
they match with the ones configured over SMBus.
Change-Id: I11459f0794278ad614aa6e16c56df1ad578fe2f8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The data payload size of PCIe root ports can be set to either 128
(default) or 256 bytes. A bigger payload size can improve PCIe data
throughput on the given port. FSP-S provides a parameter to configure
this value.
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Override the weak function mainboard_ewl_check() and select OCP_EWL.
Select IPMI_KCS_ROMSTAGE and IPMI_OCP for OCP IPMI commands which are
needed for OCP EWL driver, but they are Meta-specific BMC commands
and don't really work for AC, this change is just for a demonstration
with AC.
Note that FSP UPD promoteWarnings needs to be disabled so that
FSP won't block and can return to coreboot for EWL processing
when memory EWL type 3 error occurs.
Tested=On Intel AC, connected with a faulty DIMM can see
EWL type 3 error being generated and halted with coreboot log:
[DEBUG] Number of EWL entries 3
[ERROR] EWL type: 3 size:32 severity level:1
[ERROR] Major Warning Code = 0x29, Minor Warning Code = 0x04,
[ERROR] Major Checkpoint: 0xb7
[ERROR] Minor Checkpoint: 0x74
[ERROR] Socket 0
[ERROR] Channel 4
[ERROR] Dimm 0
[ERROR] Rank 0
[ERROR] IPMI: ipmi_get_board_config command failed (ret=3 resp=0xc1)
[DEBUG] ipmi send memory training error
[DEBUG] EWL type: 1 size:19 severity level:1
[DEBUG] 0x6392e968: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04
[DEBUG] 0x6392e978: 00 00 00
[DEBUG] EWL type: 1 size:19 severity level:1
[DEBUG] 0x6392e97b: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04
[DEBUG] 0x6392e98b: 00 00 01
[EMERG] Memory Training Error!
Change-Id: I4602ae356aa6e55ed0611b8ac9a206db127c297c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
1. Rename set_cmos_mrc_cold_boot_flag() to soc_set_mrc_cold_boot_flag
in case a certain platform may not support this via CMOS data, and
the function could in turn calls mainboard defined method in the
future. Move the code into soc_util.c.
2. Remove redundant static get_system_memory_map() from cpx/romstage.c
and call the soc_util.c one.
Change-Id: Ib7d9bed9092814658f4a0b1d6dcf3c7d79178048
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:
ACPI BIOS error (bug): Could not resolve symbol \
[\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND
BUG=b:283778468
BRANCH=skyrim
TEST=untested, but same error/fix as frostflow variant.
Change-Id: Ic498afcc8b8e0224f344f405e2f1ef6184df1d6b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75340
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:
ACPI BIOS error (bug): Could not resolve symbol \
[\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND
BUG=b:283778468
BRANCH=skyrim
TEST=untested, but same error/fix as frostflow variant.
Change-Id: Ie40541ada508acfa5771ea800249b8a57b168e3b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75339
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:
ACPI BIOS error (bug): Could not resolve symbol \
[\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot frostflow, verify error no longer present in dmesg.
Change-Id: I0b87af6b2c04f9354e6f394a8f987fa660e49134
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75338
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This is needed to support 9-series PCH-H (e.g. Z97) and Broadwell
non-ULT CPUs (for which more magic is required).
Tested on Asrock Z97 Extreme6: Boots, but ME has to be disabled so that
the system remains on after 30 seconds. Apparently, something Broadwell
MRC.bin does results in the ME being unhappy, as there is no such issue
when not using MRC.bin at all (native RAM init). S3 resume is working.
Change-Id: I7b33660099fa75c5ad46aeeda17b1215729f96c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Remove duplicated definitions of ARRAY_SIZE macro across util/ dir.
Instead of duplicates, use the one from commonlib/bsd/helpers.h file.
BUG=b:231765496
TEST=make -C util/cbfstool; make -C util/cbmem;
make -C util/intelmetool; make -C util/superiotool
Change-Id: I29b776586b4f0548d4026b2ac77095791fc9f3a3
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74474
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Grzegorz Bernacki
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Earlier the entire SPI ROM is mapped at the start of verstage and then
unmapped at the end of verstage. With CB:74606, this behavior has
changed. So unmap the hash table CBFS file after usage.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and
suspend/resume cycles for 50 iterations each. Ensured that there is no
impact to boot time.
Change-Id: I5c605f8ba8bbd571b589b3cdf91e9cc71d711c1c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75092
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the SPI ROM is mapped completely when the boot device is
initialized. That mapping remains active throughout the execution time
of PSP verstage. Every 1 MiB of mapped SPI ROM region consumes 1 TLB
Slot in PSP for use during memory mapped or DMA access. With 16 MiB of
mapped SPI ROM + FCH devices + 4 reserved TLB slots, 31 out of 32 total
TLB slots is consumed. This leaves almost no scope for future expansion.
With upcoming programs possibly using 32 MiB SPI ROM, PSP will run out
of TLB slots to support 32 MiB.
Hence instead of mapping the entire SPI ROM upfront, get the SPI ROM SMN
address during the boot device initialization. Update the boot device
region operations to map and unmap the SPI flash with the desired offset
and size using the SVC call. Then anytime a memory mapped SPI ROM access
is performed: map the required area, read the data and immediately unmap
the area. There is no update required when using CCP DMA, since the
concerned SVC call performs mapping and unmapping of the required SPI
flash area implicitly.
With these changes, maximum of 8 slots(size of RO section) might get
used at any point in time during the PSP verstage execution.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and
suspend/resume cycles for 50 iterations each. Ensured that there is no
impact to boot time.
Change-Id: Icd44ea7b2a366e9269debcab4186d1fc71651db2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74606
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently unsigned PSP verstage binary is copied from ELF file only when
required in amdfw*.rom. If a signed PSP verstage binary is supplied
while building amdfw*.rom, then it is dropped. Copy the unsigned PSP
verstage binary always so that it can be used for signing directly from
the CI build infrastructure instead of a locally built binary.
BUG=None
TEST=Build Skyrim BIOS image and ensure that the unsigned PSP verstage
is part of the build artifacts.
Change-Id: If797dcfd20aa2991f3517904ef862406b9b9875c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75334
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
