With CB:16732, EC can provide default lid switch implementation(LID0
ACPI device). Up until that point, mainboard has been providing default
switch implementation. When EC provides lid switch implementation, the
lid switch state is read from EC either through MMAP or LPC interface.
Hence there is no need to keep mainboard's LIDS ACPI object in sync with
EC's lid switch state. Use only EC's lid switch state on boards using
EC's implementation. This paves the way to remove LIDS ACPI object on
those mainboards.
BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Trigger lid open/close
events and ensure that they are detected properly through
/proc/acpi/button/lid/LID0/state.
localhost ~ # cat /proc/acpi/button/lid/LID0/state
state: open
localhost ~ # cat /proc/acpi/button/lid/LID0/state
state: closed
Ensure that the system behaves as expected based on powerd
configuration. After signin, system suspends/resumes for lid close/open.
On signin screen, system shuts down/boots for lid close/open.
Change-Id: I013574d7c21761f167ad38aeed27a419677b8000
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This to fix following error using Clang-16.0.0:
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.backlight_enable = 0x01,
^~~~
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.dock_event_enable = 0x01,
^~~~
Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
When enabled, the EC will mirror the firmware contained inside the
coreboot ROM. This allows it to be updated at the same time as
coreboot.
Enable the mirror flag if the installed EC firmware does not match
the target version or if a CMOS option, "manual_mirror_flag" is
set.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I377abbb37dc4d3e535e518a73e73969b25967daa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit b42ca4d0b2.
Reason for revert: The mirror flag "0x01" is mirror once, which
relies on the EC remembering that it's been mirrored. However, the
EC forgets this if it's been without power for 20 minutes or so.
Even if power is connected then, it'll instantly try to mirror and
it can't charge whilst doing it. It can either result in
incomplete EC firmware, or a loop where it's constantly trying to
mirror.
Change-Id: I79da9143cc63459e7e29431eff2cb14200424b37
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE.
Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when
body detection changed between lap/desk mode. However, that event is a
wake event, which resulted in spurious AP wake events being triggered
when the EC detected lap/desk mode changes while the AP was suspended.
To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was
added, which will not be a wake event. This CL adds handling for the new
event to acpi/ec.asl to switch DPTC tables when a change is detected.
BRANCH=none
BUG=b:261141172
TEST=bodydetectmode on|off, verify host event is received
Change-Id: Iabeb7891489a209f45504804355f1fa817082976
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update ec_commands.h from the EC repo at:
"8441cf4 Add host event: EC_HOST_EVENT_BODY_DETECT_CHANGE"
This is an exact copy of the EC repo's ec_commands.h with the
exception of updating the copyright message.
BUG=b:261141172
BRANCH=none
TEST=built coreboot for skyrim
Change-Id: I9892c0c3518f63d357459861e8fa1b7f5f494e68
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73258
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
This is required to prevent the EC from shutting down the system after
about 15 seconds after being turned on. If the EC doesn't receive a
command meaning "CPU OK" it assumes that the processor has failed and
flashes a diagnostic code on the keyboard LEDs to indicate this.
This also enables the keyboard and trackpad/trackpoint interfaces.
Parts of this code were derived from yet-to-be merged code in CB:44975
(ec: Add support for MEC5055 for Dell laptops) written by Iru Cai.
Tested on a Dell Latitude E6400
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: Ia420cd51e9a64be5eee4af2c0d113618575522b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59703
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update ec_commands.h from the EC repo at:
"8b6f7de2a7 fan: update fan stalled value reporting"
This is an exact copy of the EC repo's ec_commands.h with the
exception of updating the copyright message.
BUG=b:258110734
BRANCH=none
TEST=built coreboot for brya
Change-Id: I4ce15e1af40cc54a6cf2ebd6f5d5adf8953dee60
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This is a format-only change: Reformat ec_commands.h using clang-format
according to the EC repo's current formatting style.
The command is:
clang-format --style=file:$EC/.clang-format -i ec_commands.h
where $EC points to the chromeos EC repo.
The EC repo has recently adpoted the practice of formatting all files
through clang-format using its own style. So, run ec_commands.h through
the EC's clang-format so future updates don't get overwhelmed by
inconsequential style changes.
BUG=b:258110734
BRANCH=none
TEST=built coreboot for brya
Change-Id: Icbd6d00922dc5fd4c44ee109d54cea612e15db06
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Not all Chrome-EC devices have a keyboard or use Vivaldi for key
remapping, so demote the printk output when the EC doesn't support
it from ERROR to INFO. Adjust the printk text for clarity.
Change-Id: I14059f4e3e56ff891f302601d5acc1bb842cffc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72474
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all ports have retimers. Add a property to denote that a particular
port has a retimer (instead of assuming that all ports have retimers).
BUG=b:263964979
TEST=Verified on guybrush; SSDT shows retimer-switch on port1 when
device tree is updated accordingly.
Change-Id: I754323236d2912777b63cede0fce2ccf7882cfea
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71663
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When AP boots up after Cr50 firmware update and reboot, AP finds
that Cr50 reset is required for Cr50 to pick the new firmware so
it trigger Cr50 reset and power off the system, AP expects system
will power on automatically after Cr50 reset. However this is not
the case for Chromebox, Chromebox EC set AP_IDLE flag when system
is shutting down, when AP_IDLE flag is set in EC, the system stays
at S5/G3 and wait for power button presssend. It cause an issue in
factory that the operator needs to press power button to power on
the DUT after Cr50 firmware update.
This patch sends EC command to direct EC to clear AP_IDLE flag
after AP shutdown so AP can boot up when Cr50 reset.
BUG=b:261119366
BRANCH=firmware-brya-14505.B
TEST=DUT boots up after Cr50 firmware update in factory test flow
Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates initial common code structure for board_id
implementation for intel rvp platforms. Board_id helps in
identifying the platform with respect to CHROME_EC and INTEL_EC
(Windows_EC). Changes include
1. Create initial board_id.c and board_id.h
2. Modify the Makefile to include src/ec/intel directory
BUG=b:260654043
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Clang warns about structs inside a union also needing the packed
attribute.
This files is copied from the chromeec project, so it adds comment next
to the coreboot specific changes as a reference.
TEST: google/vilboz remains the same with BUILD_TIMELESS=1 and gcc.
Change-Id: I8b5233618081db86caedcb2d14870974e109ed9b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This removes the dev_index argument from the google_chromeec_reboot
API. It's always set to 0, so don't bother passing it.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
