When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and
SSFC is not set, it will treat missing SSFC as zero, so Kano needs
to set the ov2740 to 0 to avoid probing wrong mipi camera.
Before patch
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: ZYDRON_UFC=UFC_MIPI_HI556
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: STYLUS=STYLUS_PRESENT
After patch
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>I2C: 00:20 disabled by fw_config
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: STYLUS=STYLUS_PRESENT
BUG=b:262939431
TEST=Boot on kano and check functional with ov2740 camera.
Change-Id: I46fac6c820d6006956680a07198db82225630905
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This is support for adding legacy VGA support into romstage.
Support for this is being provided by libgfxinit.
The current use case allows us to initialize the display
before memory init (prior to physical memory init) to inform
the user when lengthy memory training is needed.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=VGA code compiles for romstage
Change-Id: I81309871e8db71657b2a9816708141f121d767d3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70278
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables the stage cache to save boot time.
Note: S3 is not POR for Intel MTL mobile skus.
Boot time is reduced by ~8ms.
Boot time before:
4:end of romstage 1,391,225 (13,724)
100:start of postcar 1,403,339 (12,114)
Boot time after:
4:end of romstage 1,380,262 (5,618)
100:start of postcar 1,392,323 (12,060)
Change-Id: I9775fc628f345a514894f30435a374e2ffa057c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The patch addresses Intel heterogeneous cores as `Efficient` and
`Performance` cores instead of `small` and `big` cores. It is to ensure
coreboot code has uniform reference to the heterogeneous cores. So, the
patch renames all `small` and `big` core references to `efficient` (eff)
and `performance` (perf) cores respectively.
TEST=Build the code for Brya and Rex boards
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71639
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add below mentioned functions:
is_sgx_configured_and_supported():
Checks if SGX is configured and supported
is_keylocker_configured_and_supported():
Checks if Key Locker is configured and supported
check_prm_features_enabled():
Checks if any of the features that need PRM are configured
and supported. As of now SGX and Key Locker are the only
features that need PRM.
Also, call check_prm_features_enabled() from get_valid_prmrr_size()
to make sure PRM dependent features are enabled and configured before
returning PRMRR size.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
To support an RPL SKU on omnigul, omnigul must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for omnigul so that it will use the RPL
FSP headers for omnigul.
BUG=b:263060849
BRANCH=None
TEST=FW_NAME=omnigul emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Change-Id: If3cfbaeff0472012cb8f30ed8fff3bf5cac23f85
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Change-Id: I6a0afb04bea4940e13ea62c2cd0a09500b8b5335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71702
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Although S3 is supported on nissa, only S0ix is used on user devices,
so we can ignore optimising the S3 resume time. Disable the stage
cache to save boot time at the cost on increasing the S3 resume time.
Boot time is reduced by ~6 ms. This is mostly from adding postcar to
the stage cache, which is slow since TSEG is not cached in romstage.
Adding ramstage and FSP-S take negligible time.
The S3 resume time is increased by ~89 ms total from loading and
decompressing ramstage and FSP-S.
Boot time before:
3:after RAM initialization 573,295 (931)
4:end of romstage 583,569 (10,274)
100:start of postcar 587,729 (4,160)
Boot time after:
3:after RAM initialization 571,527 (830)
4:end of romstage 575,712 (4,185)
100:start of postcar 579,866 (4,153)
S3 resume time before:
101:end of postcar 368,904 (0)
10:start of ramstage 369,165 (260)
971:loading FSP-S 385,742 (16,577)
30:device enumeration 407,105 (21,362)
S3 resume time after:
101:end of postcar 363,101 (0)
8:starting to load ramstage 363,101 (0)
15:starting LZMA decompress (ignore for x86) 382,802 (19,701)
16:finished LZMA decompress (ignore for x86) 431,620 (48,817)
9:finished loading ramstage 431,850 (230)
10:start of ramstage 431,927 (76)
971:loading FSP-S 448,357 (16,430)
17:starting LZ4 decompress (ignore for x86) 474,420 (26,062)
18:finished LZ4 decompress (ignore for x86) 474,627 (206)
BUG=b:247940538, b:192032803
TEST=Boot and S3 suspend/resume on craask
Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71677
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
On recent Intel ChromeOS devices, although S3 is still supported, only
S0ix is used on user devices, so we don't care about optimising S3
resume time. Disabing the stage cache saves boot time at the cost of
increasing the S3 resume time. E.g. on nissa this reduces boot time by
6 ms and increases S3 resume time by 89 ms.
BUG=b:247940538, b:192032803
TEST=Build and boot on nissa with MAINBOARD_DISABLE_STAGE_CACHE
selected.
Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Updating from commit id 196b0843e9 :
to a09b792e6a : Makefile: Remove old include directories
This brings in 9 new commits.
Fix:
cc1: error: firmware/lib/cryptolib/include: No such file or directory [-Werror=missing-include-dirs]
cc1: error: firmware/lib20/include: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I292d3a4046c1a1890a640747cbbd00e79e5e56b4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71582
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch will enable Kconfig SOC_INTEL_CSE_LITE_SKU option required
to enable CSE-Lite SKU for MTL-RVP. On enabling the respective Kconfig
option, CSE reboots the system into CSE_RW FW region on cold reboot.
BUG=b:224325352
TEST=Able to boot intel/mtlrvp to ChromeOS and also able to observe
CSE boot to RW FW region as part of coreboot console log,
localhost ~ # cbmem -c | grep cse
[DEBUG] cse_lite: Number of partitions = 3
[DEBUG] cse_lite: Current partition = RW
[DEBUG] cse_lite: Next partition = RW
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I325405cc304d245871396317c11ac7a5b062a5bd
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71638
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
H58G56BK7BX068 0 (0000)
K3KL9L90CM-MGCT 1 (0001)
H58G66BK7BX067 1 (0001)
MT62F2G32D4DS-026 WT:B 1 (0001)
BUG=b:263296326, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I4f00d444bd59443ecba29c6c155d676bab7a3d82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Create the markarth variant of the skyrim reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:262092858
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_MARKARTH
Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82
Signed-off-by: Chao Gui <chaogui@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
BUG=none
TEST=Verify presence of subsystem ID for fast_spi device on google/rex.
lspci output before this patch:
00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23]
lspci output after this patch:
00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23]
Subsystem: Intel Corporation Device [8086:7e23]
Note: UPD SiSkipSsidProgramming was set to 1 for above test.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I08c7a5a3fdc7389b315e85180c16d1ec335fbba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP.
Since we use RPL FSP and it will support ADL as well, we rename
"Gaelin4ADL" to "Gaelin".
BUG=b:258603624
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot
Cq-Depend: chrome-internal:5227091, chromium:4113361
Change-Id: Ie7349f3670aeec166228e7df55300cd30d0ca16c
Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Fix:
CC romstage/mainboard/amd/pademelon/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
CC romstage/mainboard/amd/gardenia/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
CC romstage/mainboard/google/kahlee/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
CC romstage/mainboard/google/kahlee/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
