This patch makes the SoC specific callback code more readable by adding
`soc_` prefix into the `get_dptf_platform_info()`.
In nutshell this patch renames `get_dptf_platform_info()` to
`soc_get_dptf_platform_info()`.
TEST=Able to build Google/Rex without any compilation issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
dapc_init flow is the same on MT8186, MT8188 and MT8195. So move this
function to common/devapc.c
TEST=emerge-corsola coreboot; emerge-cherry coreboot;
emerge-geralt coreboot
TEST=devapc log is shown as expected and the system boots to kernel
Change-Id: I979c3a3721a82d40c9e2db7fbe62e14a9bbd53d8
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71137
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
It's true that vbnv_udc_enable_flag() is called after vbnv_init()
(that's why the assertion was added). However, the former is called in
the ramstage, while the latter in verstage. This means that
vbnv_initialized will be false in ramstage, which leads
to the assertion failure:
[EMERG] ASSERTION ERROR: file 'src/security/vboot/vbnv.c', line 88
Since the ctx->nvdata will be restored in ramstage (by vb2api_reinit()),
simply remove the assertion. So, the patch drops assert call from
vbnv_udc_enable_flag() function.
TEST=Verify Rex system boots to OS without assert error.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I49022155239febd5c5be5cf2c5eca2019ca61c12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as kano is using a converged firmware image.
BUG=b:253337338
BRANCH=firmware-brya-14505.B
TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
disable hardware write protect and software write protect,
flash and boot kano in end-of-manufacturing mode to kernel.
Cq-Depend: chrome-internal:5246998, chromium:4119763
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: I30ab7d829a6cb45b4e0cd38747501ba0eb6bd6cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71175
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adapted from WIP (and now abandoned) patches CB:25334, 26308, 26309.
Update the nhlt_soc_add_*() methods for max98373, max98927, and rt5514
codecs to program the render and feedback slot numbers as appropriate.
TEST=boot Windows on google/eve, atlas, nocturne, and rammus. Verify
audio functional with both Google project campfire drivers as well as
coolstar's AVS audio drivers.
Change-Id: Ib8c6e24ba539e205bd5bbd856ecff43b2c016c2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Adapted from WIP (and abandoned) patch CB:25334, this patch:
1. Ensures SSP endpoint InstanceId is 0
2. Adds capability_size parameter at the end of the nhlt
3. Adsd more config_type enum values to accommodate feedback stream
4. Programs virtual_slot values for max98373, max98927,
and rt5514 nhlt files
5. Adds NHLT feedback_config parameters
Default feedback configs are added here to the max98373, max98927, and
rt5514 codecs; in a follow-on patch, these will be overridden at the
board level.
TEST=tested with subsequent patch
Change-Id: I59285e332de09bb448b0d67ad56c72a208588d47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Contrary to mc_ehl2, which this variant is based on, this board
doesn't contain the TI XIO2001 PCIe-to-PCI bridge, which makes the
attempts to modify the bridge's registers unnecessary.
Change-Id: I6597ceb78e4c790c08a0dfa9535dece33a8f95b8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70854
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch from using ACPI "probed" flag to "detect" flag for all i2c
touchscreens and digitizers. This removes non-present devices from the
SSDT and relieves the OS of the burden of probing.
Test: build/boot Windows/Linux on various octopus variants, verify
touchscreens/digitizers functional, dump ACPI tables and verify only i2c
devices actually present on the board have entries in the SSDT.
Change-Id: I67c5bbae42e96ae21d37309e382b635321e6ef01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63214
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: I13bc6920a0dfaf769091b1764a7584902d1f85d6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63213
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For octopus variants with a touchscreen/digitizer, drive the enable and
reset GPIOs high in romstage, then disable the reset GPIOs in ramstage.
Where available, only set the GPIOs for SKUs which have a touchscreen.
This will allow coreboot to detect the presence of i2c touchscreens
during ACPI SSDT generation (implemented in a subsequent commit).
TEST=tested with rest of patch train
Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63212
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.
TEST=tested with rest of patch train
Change-Id: I4a8e11945ae64b000051989089e0ebae22896c6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70905
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to report previous PSP boot failure to verified boot. This
is required specifically on mainboards where the signed AMDFW blobs are
excluded from vboot verification.
BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Corrupt either
one of SIGNED_AMDFW_A/B sections or both the sections to ensure that the
appropriate FW slot is chosen.
Cq-Depend: chromium:4064425
Change-Id: Iada0ec7c373db75765ba42cb531b16c2236b6cc3
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70382
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an SVC command to get the previous boot status. If there is any
pre-x86 boot failure in the previous boot cycle, PSP stores it in warm
reset persistent register and triggers a warm reset. PSP verstage on the
subsequent boot gets the previous boot status and reports any failure to
the vboot before a FW slot is selected.
BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure
scenario by corrupting certain firmware blobs and observe that PSP
reports the failure boot status. On a normal boot, observed that PSP
reports successful boot.
Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables building ChromeOS for mtlrvp.
Patch includes,
1. Add cros_gpios for mtlrvp
2. Add chrome OS configuration in Kconfig
3. Add Chromeos.c
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train (CB: 69886)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ia428941bd8269714c3edca6c7b0c2a3fbf08bd75
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70724
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Power resource for Bluetooth device is not configured correctly in the
device tree. Fix Bluetooth devicetree configuration.
BUG=b:262785310
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the DUT is able
to connect to a Bluetooth headset.
Change-Id: Id980424349537be35860dec04cc823d419cefe2f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71068
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
smm_relocation_handler is run for each thread but IA32_SMRR_PHYS_BASE
and IA32_SMRR_PHYS_MASK are core scope, need to avoid writing the
same MSR that has been locked by another thread.
Tested=On OCP Crater Lake, rdmsr -a 0x1f3 can see all cores set the lock
bit.
Change-Id: I9cf5a6761c9a9e1578c6132ef83e288540d41176
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This patch adds files required for ramstage and SMM.
1. Add file required for ramstage (mainboard.c)
2. Add smihandler.c for SMM
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I377c4ff954a900c7b5193d7cab5554c6c02573ee
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70723
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch will initialize EC for mtlrvp which includes,
1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC)
2. Add respective ACPI configuration
3. Add ec.c required for ramstage
4. Program EC ranges as part of devicetree.cb
5. Enable VBOOT in Kconfig
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with
CHROME_EC using subsequent patches in the train
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 2047412:
2022-11-29 17:52:03 +0800 - (Elkhart Lake MR5 FSP)
to commit id 6f2f17f:
2022-12-14 12:36:46 -0700 - (Deleted old Release Notes and Integration Guides)
This brings in 6 new commits:
6f2f17f Deleted old Release Notes and Integration Guides
3868f73 Updated for SGXFlex - New UPDs available
a649f0f Whitley FSP 2.2.0.3A
f99be62 Merge branch 'master' of https://github.com/intel/FSP
1787bc7 Updated IoT ADL-PS MR1 (3404_00) FSP
1e833b0 Elkhart Lake MR5 FSP
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1dbd85ef06b057305428d42dd6cd6de0f2618439
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
