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Author SHA1 Message Date
Sridhar Siricilla
b739fd287d soc/intel/common: Drop unreferenced DP related macros 
The patch drops the unreferenced DP related timeout macros.

TEST=Build code for Rex

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3f4c7733a92d1b7cb107410fedaca20ede040050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-16 17:06:52 +00:00
Frank Chu
0cb7e614d0 mb/google/brya/var/marasov: Update gpio table for EVT 
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id5a73126737a3abbe6f0ef37276ce20f687b47fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70236
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
 2022-12-16 17:05:53 +00:00
Frank Chu
93197d20b6 mb/google/brya/var/marasov: Disable unused PCIE8 for s0ix 
Disable unused PCIE8 for fix system can not enter S0ix completely.

BUG=b:261915226
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I06f8bd06e1fe92c03bd5625a41469830ce37a11c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70660
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-12-16 17:05:22 +00:00
Liju-Clr Chen
26a8dea551 mb/google/geralt: Revise the naming of MIPI PWM control GPIO 
Rename the MIPI PWM control GPIO to be consistent with the schematic.

BUG=b:244208960
TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB

Change-Id: I6a3368d438cb50b257992260d1388f0b7e0f5ace
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70822
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2022-12-16 17:05:05 +00:00
Bo-Chen Chen
f57155bca4 mb/google/geralt: Pass GPIOs to allow backlight control in payloads 
There are two ways to control backlight in geralt:
1. MIPI/eDP panel => control backlight via the GPIOs.
   (`backlight chip enable` and `PWM dimming control`)
2. eDP OLED panel => enable backlight via `backlight chip enable` and
   control dimming over AUX.

For MIPI/eDP panels(#1), both "backlight enable" and "PWM control" GPIOs
will be passed from coreboot. For eDP OLED panel(#2), only the
"backlight enable" GPIO will be passed. If depthcharge successfully gets
the GPIOs, it will use them to control backlight.

BUG=b:244208960
TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB

Change-Id: I866fa219722241008e2b0d566b29edf2f6d9321f
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70744
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-16 17:04:35 +00:00
Frank Chu
de4727aecc mb/google/brya/var/marasov: Enable ELAN touchscreen 
Correct touchscreen setting to make touchscreen function workable.

BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=Built and verified touchscreen function

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ia98deae65ef0e2f501457331144b044e07431a3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-16 17:04:14 +00:00
Felix Held
76364fb66b drivers/i2c/designware/dw_i2c: handle bus < 0 in dw_i2c_dev_transfer 
dw_i2c_soc_dev_to_bus will return -1 if it failed to find an I2C bus
number for a device. In this case return -1 instead of implicitly
casting the -1 to an unsigned int and passing that as bus number to
dw_i2c_transfer. The dw_i2c_base_address call inside _dw_i2c_transfer
already ended up handling this error case correctly, but better handle
the error more directly.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06b6005cee0c5c43855cb5b388a9911fc286c984
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-16 15:33:00 +00:00
Felix Held
d832bda32b soc/amd/common/block/i2c: don't call die() when MMIO address is NULL 
There's no need to call die() in the case that the MMIO address of the
I2C controller is NULL, so handle this case by returning a failure
instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12c143916ad551c56cc4ff75ae23754018817505
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-16 15:32:02 +00:00
Elyes Haouas
f3c107eb01 soc/intel/apollolake/acpi/northbridge.asl: Fix comment 
This fixes the following error:
In file included from src/mainboard/siemens/mc_apl1/dsdt.asl:21:
src/soc/intel/apollolake/acpi/northbridge.asl:15:12: warning: '/*' within block comment [-Wcomment]
                PXEN,   1,      /* Enable */
                                ^

Change-Id: I1173eed69847f4c3b307ce96d76fb7185dc2f85c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70767
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
 2022-12-16 06:15:27 +00:00
Karthikeyan Ramasubramanian
f2dcd9dd81 security/vboot: Update vbnv_init signature 
If the temporary nvdata storage inside the vboot context is already
initialized then return immediately without reinitializing from the
backup NV storage. This allows vbnv_init to be called more than once.

Also the check to enable USB Device Controller (UDC) happens after
NVdata is initialized. Hence the nvdata in vboot context can be used
instead of reading from the backup storage again.

BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim.

Change-Id: Id72709e2fc3fe6a12ee96df8df25e55cf11e50a7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-12-16 01:23:03 +00:00
Felix Singer
d901077335 ec/kontron/it8516e/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I16890206d517f0455d29c1642cbbe642a3312481
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70679
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-16 00:59:41 +00:00
Felix Held
ca261091eb cpu/x86/mtrr: rename local cpu_idx variable and make it const 
After the previous patch this local variable is no longer the mpinit CPU
index, but the LAPIC ID, so rename it. Since it will only be set once,
it can also be marked as const.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4fad4e1095478213727bee8586852f9d5a7d18e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70798
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
 2022-12-16 00:30:12 +00:00
Subrata Banik
08529918fc mb/google/rex: Add support for WWAN over USB3 
This patch connects USB3_PCH_*_WWAN_* to USB32_2 as per Proto 1
schematics dated 12/14/2022.

TEST=Able to build Google/Rex.

Change-Id: Ie04c79ff5c231527e3d5f63a5cc553ec39c46914
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-15 18:08:04 +00:00
Subrata Banik
bc6a305f82 mb/google/rex: Modify the PIN name as per schematics 
This patch updates the GPIO PIN name as per Proto 1 schematics dated
12/14/2022.

TEST=Not code change, just updated the comment section.

Change-Id: Ic076ab35689fd2afb7c18eff065a90b9464a6b1d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-15 18:07:45 +00:00
Eran Mitrani
4c9440c673 soc/intel/{adl, common}: provide a list of D-states to enter LPM 
This was done previously for ADL. moving the code to common so
it can be leveraged for other platforms (e.g. MTL)

TEST=Built and tested on anahera by verifying SSDT contents

Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-15 16:53:51 +00:00
Frank Wu
d27cd2a328 mb/google/skyrim/var/frostflow: Update SPD file for H9JCNNNFA5MLYR-N6E 
Update RAM ID table because H9JCNNNFA5MLYR-N6E is using spd-4.hex
instead of spd-9.hex.
Reserve RAM ID 3 for it, so the RAM ID table remains the same.

BUG=b:261530632
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot chromeos-bootimage
Then boot devices successfully

Change-Id: I1b683168310f74a07d246af8618b977cce32287a
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-15 14:28:11 +00:00
Frank Wu
3a4e201a21 spd/lp5: Update memory configuration of H9JCNNNFA5MLYR-N6E 
Update bitWidthPerChannel in memory_parts.json and re-generate the SPD.
Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E.

BUG=b:261530632
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-15 14:28:02 +00:00
Elyes Haouas
315d3264b6 treewide: Remove unused 'include <arch/io.h>' 
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2022-12-15 13:37:41 +00:00
Stanley Wu
8d728c2090 mb/google/nissa/var/pujjo: Modify WWAN warm reset sequence 
pujjo support FM101 WWAN, add delay of FCPO# to meet warm reset toff
minimum 500ms requirement.

BUG=b:260380268
TEST=Build and boot on pujjo

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I63e599e76bd8a15ca44717823411576fa4df1c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
 2022-12-15 13:36:18 +00:00
Subrata Banik
5dfec71829 soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions 
As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM
Configuration

+-----------------------+-------------------------------+
|    Field Description  |       ASPM Support            |
+-----------------------+-------------------------------+
|     00b               |       No ASPM support         |
+-----------------------+-------------------------------+
|     01b               |       L0s Supported           |
+-----------------------+-------------------------------+
|     10b               |       L1 Supported            |
+-----------------------+-------------------------------+
|     11b               |       L0s and L1 Supported    |
+-----------------------+-------------------------------+

100b aka 0x4 is added by FSP to allow auto configuration (to avoid
conflicting with the PCI specification defined values).

Additionally, changed enum definition which is now meeting the FSP expectations better.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-15 08:11:30 +00:00
Kapil Porwal
0f15030700 mb/google/rex: Add RTD3 support for discrete wifi module 
BUG=none
TEST=Build and boot to the OS on google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2c5bac880e7dbc2ec14376c5cee3c13363bab377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70444
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-15 08:10:19 +00:00
Karthikeyan Ramasubramanian
dee52d962d Update vboot submodule to upstream main 
Updating from commit id 148e5b83:
    Makefile: Fix and simplify the RUNTEST test wrapper

to commit id 196b0843:
    create_new_keys: use single AP RO Verification root key pair

This brings in 30 new commits.

Change-Id: Iedfc6cf0ff2dc1913a7a41a4302dc1951abf8a8a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2022-12-15 03:13:55 +00:00
Elyes Haouas
45d818b4ab nb/intel/sandybridge/sandybridge.h: Remove unnecessary guard 
__ACPI__ is covered through __ASSEMBLER__.

Change-Id: I6a637e63c6bbe4af7cd52be1893e47d6b5967886
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70697
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-15 03:13:11 +00:00
David Wu
4f29739be3 mb/google/brya/var/zydron: Enable Fast VMode for zydron 
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.

BUG=b:252966799
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log

Change-Id: I175f7f39d6115d1f082575393c45734c7b02e346
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-15 03:12:19 +00:00
Bora Guvendik
8c46232005 soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode 
Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.

BUG=b:235863379
TEST=Boot in compliance mode, check FSP settings

Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-12-15 03:11:24 +00:00
Felix Held
447f5777aa cpu/x86/mtrr: use lapicid instead of cpu_index calls 
The cpu_index function can't be used before mpinit, so use lapicid calls
instead. This fixes the regression introduced by commit 4c3749884d
("cpu/x86/mtrr: Print cpu index number when set up MTRRs for BSP/APs")
and also reverts also commit b3261661c7 ("cpu/x86/mtrr/mtrr: fix
printk format strings"), since lapicid returns an unsigned int while
cpu_index returns an unsigned long.

TEST=Mandolin boots again and doesn't fail when it first tries to print
the MTRR configuration

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0d226704051ab171891775a618ce7897b74fde16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70797
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2022-12-15 03:10:08 +00:00
Julius Werner
2cf2bd8197 mem_chip_info: Fix potential overflow 
The calculation for mem_chip_info_total_density_bytes() may already
overflow in the intermediate 32-bit calculations before being assigned
to the 64-bit result variable. Fix that.

Fixes Coverity issue: CID 1501510

BRANCH=corsola

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I73da014c953381974c6ede2b17586b68675bde2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2022-12-15 02:53:45 +00:00
JasonNien
4a0e5e4741 mb/google/skyrim: Enable PCIe RTD3 support 
Add PCIe RTD3 support for Skyrim

BUG=b:245550573
TEST=Boot/Reboot cycles and Suspend_stress_test 10 times

Signed-off-by: JasonNien <finaljason@gmail.com>
Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 21:31:40 +00:00
Fred Reitberger
267edecccb soc/amd/morgana/Kconfig: Remove TODO after review 
Remove more TODO comments after reviwing against morgana ppr #57396, rev
1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7fd9666a69d9a2b0902fa28ab0af0187198297ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70466
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-14 19:39:10 +00:00
Arthur Heymans
8f95f74eb2 util/cbfstool: Fix building with clang & -Wshadow 
Clang -Wshadow is more rigorous than GCC and picks a shadowing of the
optarg global variable in /usr/include/bits/getopt_core.h .

TESTED: builds with both gcc and clang.

Change-Id: Ifc362c84511abb6a000671f03498e841d7747074
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70508
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-12-14 18:31:55 +00:00
Felix Held
c4f5241e66 soc/amd/common/block/espi_util: drop unneeded check in espi_get_config 
Since soc_get_common_config will either return a valid pointer or cause
a linking error, this function will also return a valid pointer or cause
a linking error, so no need for additional runtime checks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99661247b9f8f47a708e3a6ff3f9e5359b505509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70739
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2022-12-14 17:58:08 +00:00
Felix Held
993092039b soc/amd/*/config: drop invalid comment 
Since commit 28e61f1634 ("device: Use __pci_0_00_0_config in
config_of_soc()") config_of_soc() was changed form being an actual
function to a macro for the __pci_0_00_0_config struct pointer generated
by util/sconfig. This change didn't only improve linker optimizations,
but also turned runtime errors into link-time errors, so it's guaranteed
that __pci_0_00_0_config won't be NULL and config_of_soc() won't
"return" NULL.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id99ceaa9f7a70788da3f3068fb3da92d34fb6361
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70732
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2022-12-14 17:57:45 +00:00
Felix Held
687ec6bd72 soc/amd/common/block/espi_util: make espi_set_initial_config non-fatal 
Improve the espi_set_initial_config implementation so that a failure in
there due to an invalid configuration won't call die() and stop booting
at this point, but return an error to the caller so that the rest of the
eSPI configuration will be skipped.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97f730778a190c4485c4ffe93edf19bcbaa45392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2022-12-14 17:07:19 +00:00
Felix Held
84429e092f soc/amd/common/block/lpc/espi_util: make eSPI pin setup failure nonfatal 
Improve the eSPI pin configuration setup so that a failure in there
won't call die() and stop booting at this point, but return an error to
the caller so that the rest of the eSPI configuration will be skipped.
This will prevent an early boot failure if the EC is missing or the eSPI
interface is in a non-functional state. Also slightly shorten the
function names so that the code still fits into 96 chars.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice2d3a791d6a464eff4fb69d02aeca0bfe580be2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70730
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
 2022-12-14 16:05:50 +00:00
Arthur Heymans
4f2b5a5dbd device/cpu_device.c: Zero initialize struct 
Don't rely on this being 0.

Change-Id: I7c0d16b6a265bf9c7abcfdf2f18a43706ee03ea1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69752
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-14 13:52:00 +00:00
Arthur Heymans
db65dd60fb cpu/x86/mp_init.c: Improve AP entry point 
Make sure that a pointer exists before dereferencing it.

Change-Id: I1a9833bb9686451224249efe599346f64dc37874
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-14 13:51:40 +00:00
Jakub Czapiga
3c8a3d1295 tests/Makefile.common: Allow to disable test framework with parameter 
Test framework can be used as a base for other test-like utilities - for
example look at screenshoot utility in depthcharge. Sometimes CMocka is
not required and even makes things problematic. Thanks to this patch one
can set -no_test_framework parameter to instruct framework not to
include and link selected test against CMocka library.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I01dc7c6c50e6ae2f7f71bd6752c2d5f2cc7c3cdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
 2022-12-14 13:37:39 +00:00
Sridhar Siricilla
f9ee35ea34 soc/intel/common: Add helper function to get DP mode 
The patch adds helper function to get the DP mode.

TEST=Build the code for Rex

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I02ed1f818e77c37ead8ce962fa12fddfdc8efeb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-12-14 13:35:36 +00:00
Arthur Heymans
e64b8ac1e7 cpu/intel/206ax: Fix generating C state entries 
The struct device passed to this function is the cpu cluster and not
individual lapic. This fixes a regression introduced by
cdb26fd (cpu/intel/model_206ax: Remove fake lapic device)

Change-Id: I586e13a723303b8d639d526a175bd6828465a607
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2022-12-14 13:31:09 +00:00
Subrata Banik
d34364bdea soc/intel/alderlake: Utilize CPU_BCLK_MHZ over dedicated macro 
This patch drops the redundant macro to define CPU BCLK and instead
uses `CPU_BCLK_MHZ` config to calculate the
`smbios_cpu_get_max_speed_mhz`.

TEST=Able to see max cpu speed is correct in smbios table while trying
on Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5167f3a513c074b9e6986c960e1bcced65f1264c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70676
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-14 07:03:16 +00:00
Subrata Banik
ba6e66328b soc/intel/meteorlake: Drop NEM support 
This patch drops NEM support from MTL and enables eNEM support.

BUG=b:217130861
TEST=Able to build and boot Google/Rex in eNEM mode.

Change-Id: I6ef915ec0caf0d95b488602950b0b25958ec4cbd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70673
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-14 07:02:31 +00:00
Subrata Banik
43004211e2 soc/intel/meteorlake: Add required configs to enable eNEM 
This patch combines all required configs under one umbrella config
named `METEORLAKE_CAR_ENHANCED_NEM`.

MTL SoC to select this config if default NEM (INTEL_CAR_NEM) is not
selected.

BUG=b:217130861
TEST=Able to build and boot Google/Rex.

Change-Id: Iceab7cdf2973f3858d4aa83fb431ba832c0868d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70672
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-14 07:01:59 +00:00
Subrata Banik
8e158597f9 soc/intel/meteorlake: Reorg TCSS related configs 
This patch moves all required TCSS related configs under one umbrella
config named `SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT`. This effort will
help in future to deselect the TCSS support for MTL SoC SKUs.

TEST=Able to build and boot Google/Rex.

Change-Id: Id86e52842d2f8ab4dbec4a8776791e1266b94298
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70671
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-14 07:01:48 +00:00
Subrata Banik
b5fc0c4088 drivers/wwan/fm: Fix typo 
This patch fixes a typo by adding `Arg0 = 0` to define warm reset.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I92b81697a254c9dab127b200174d32554db1b5cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70721
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-14 06:51:15 +00:00
Subrata Banik
6ed431589b vc/intel/fsp/mtl: Update header files from 2404_00 to 2431_80 
Update header files for FSP for Meteor Lake platform to
version 2431_80, previous version being 2404_00.

FSPM:
1. Address offset changes

FSPS:
1. Address offset changes

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id192598e2ef57b9d7dacfbfd086a67593a2cd12e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-14 06:47:47 +00:00
Subrata Banik
10929ef008 soc/intel/meteorlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable 
This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.

This patch is backported from
commit fad1cb062e (soc/intel/alderlake:
Fill ucode loading UPD if USE_FSP_MP_INIT enable).

Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-14 06:35:11 +00:00
Subrata Banik
b25aeb5937 soc/intel/meteorlake: Remove FIXME as SkipMpInit UPD has deprecated 
This patch drops deprecated FSP UPD `SkipMpInit` as Intel MTL FSP
doesn't like to allow an option for boot firmware to perform CPU feature
programming being independent of FSP.

Change-Id: I6447937838ab91551d172936cbb4201ea86a614b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70557
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-14 06:34:16 +00:00
Subrata Banik
95fc5d776a soc/intel/meteorlake: Drop enable_bios_reset_cpl() function 
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset
CPL before performing Graphics PM init (as part of FSP-S), hence,
enable_bios_reset_cpl() function getting called inside systemagent.c
is meaningless.

Also, drop 1ms delay after setting the BIOS reset CPL.

This patch is backported from
commit 3f980ca7be (soc/intel/alderlake:
Drop enable_bios_reset_cpl() function).

Change-Id: Ia31867153b3b5f132c393a605c44616acfd7a34b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70556
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-14 06:33:23 +00:00
Subrata Banik
decb9717ce soc/intel/meteorlake: Enable VMX and VTD 
Drops the `FIXME` comment and relevant code as this patch enables
VMX and VTD.

This patch also fixes the problem of additional reboot on every warm
boot due to overriding the CPU soft-strap.

TEST=No extra reboot seen while issuing warm reset from kernel
console.

without this patch:
950:calling FspMemoryInit		1,225,259 (20,537)
951:returning from FspMemoryInit	10,334,707 (9, 109,447)

with this patch:
950:calling FspMemoryInit		1,225,259 (20,537)
951:returning from FspMemoryInit	1,334,707 (109,447)

Change-Id: Ib130698e7255876c5a12abc93dd7d8a34dfae968
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70553
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-14 06:33:09 +00:00
Eran Mitrani
988d3eefa6 mb/google/hatch/dratini: increase power enable to reset deassert delay 
With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.

TEST=tested on dratini device and observed the issue is resolved.
BUG=b:260253945

Change-Id: I5c3edbc6ac90d5042c2d3c5b01573d4bb1ea676d
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70666
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-14 03:46:09 +00:00