This finds all the boards using a specified Kconfig option and runs both
CrOS and non-CrOS abuilds on them to make sure they're working.
Nobody wants to run the full what-jenkins-does build on their host
machine. Hopefully this can help get some tests run locally before
pushing to coreboot.org.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The deadlock prevention is also needed with CONFIG_X2APIC_RUNTIME when
the cpu is in x2apic mode.
TESTED: Fixes SMI generation on xeon_sp hardware with
CONFIG_X2APIC_RUNTIME.
Change-Id: I6a71204fcff35e11613fc8363ce061b348e73496
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
DTTS is Dynamic Thermal Table Switching Proposal.
DTTS needs one bit to save the body detection result from EC.
Define mode change STTB bit for Desktop (1) and laptop (0).
This bit is Switch thermal table by body detection status.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit eb76a455cd
and applies minor fixes to make it build again.
PARALLEL_MP was working prior to board removal and no
relevant SMI handlers were implemented. So NO_SMM choice
is now selected.
Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the \_SB scope, but those
are defined inside the \_SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.
TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the \_SB scope
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
This code was never tested with SSE enabled. Now qemu enables it and
FX_SAVE encroaches on the save states. Without SSE enabled the handler
just happened to be aligned downwards enough to have the save states
fit. With SSE enabled that's not the case. The proper fix is to give the
code setting up stubs the right base address, which is the same as for
the TSEG codepath.
Change-Id: I45355efb274c6ddd09a6fb57743d2f6a5b53d209
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69233
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
In Linux, the I2C speed defaults to 400 kHz if there is no device
registered in ACPI which requests a different speed. Due to board
limitations (layout, bus load), 400 kHz are too fast which results in a
timing violation. Therefore, add a dummy I2C device to both used I2C
buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus
speed in Linux accordingly.
Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
According to measurements Elkhart Lake seems to drive the internal I2C
controllers with 100 MHz instead of the common 133 MHz. The datasheet
itself is quite vague on this definition, just one place mentions that
it is 100 MHz (register description for offset 0x94).
This patch changes the I2C controller base frequency to 100 MHz. The
verification was done by measuring the set up resulting I2C clock for
both 100 and 400 kHz.
Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
There are SoCs (for instance Intel Elkhart Lake) that do use 100 MHz as
the base clock for I2C controllers. To support them properly add a
frequency setting for 100 MHz to the designware I2C controller driver.
Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
On certain mainboards due to hardware design limitations, certain SPI
Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to
override SPI read modes in boards which do not have hardware
limitations. Currently there is an API to override SPI fast speeds.
Update this API for mainboards to override SPI read mode as well.
BUG=b:225213679
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~25 ms with 100 MHz SPI speeds.
Before:
11:start of bootblock 688,046
14:finished loading romstage 30,865
16:FSP-M finished LZMA decompress (ignore for x86) 91,049
Total Time: 1,972,625
After:
11:start of bootblock 667,642
14:finished loading romstage 29,798
16:FSP-M finished LZMA decompress (ignore for x86) 87,743
Total Time: 1,943,924
Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
SX9324 driver is updated per Linux's documentation found at
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml
Supporting logic for the deprecated SX932x driver is hence guarded by
DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
This patch by itself does not introduce functional changes to any board.
The legacy SX932x Linux driver never reached upstream Linux and is only
available in ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted
a different implementation named SX9324 and has been available since
5.4. Ideally all variants should adopt the new driver; however, during
the transition phase, coreboot must support both drivers. It is better
to have a single firmware build that can work with both Linux kernel
drivers by specifying both sets of properties. Legacy driver support
should be deleted once all variants finish migration.
BUG=b:242662878
TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy
SX932x driver are identical w/ and w/o this patch
(Tested on Craask and Nivviks)
Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69192
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add Fingerprint SPI, and power-off FPMCU during romstage.
For reference see CL:66915 for a similar change to Brya's power sequence
SHA: 2b523ce631 ("Invoke power cycle of
FPMCU on startup")
TEST=Tested on Rex - setup and logged in using fingerprint
Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch introduces support signing and verification of firmware
slots using CBFS metadata hash verification method for faster initial
verification. To have complete verification, CBFS_VERIFICATION should
also be enabled, as metadata hash covers only files metadata, not their
contents.
This patch also adapts mainboards and SoCs to new vboot reset
requirements.
TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel FSPs of XEON server platforms define FSPX_CONFIG
instead of FSP_X_CONFIG, which is expected by coreboot.
Re-define in the common code.
Update coreboot code to use FSP_X_CONFIG consistently.
Tested=On OCP Delta Lake, boot up OS successfully.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The functions create_bpdt_hdr and create_cse_layout
in bpdt_1_6.c are defined to return pointers but
not integers as was previouly implemented.
Reported-by: Coverity(CID:1469323)
Reported-by: Coverity(CID:1469353)
Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: Idb78d94be7a75a25ad954f062e9e52b1f0b921dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This patch replaces static index 0 for PMC read resources with PCI
configuration offset 0x10 (PWRMBASE).
TEST=Able to build and boot Google, Rex to OS.
Without this change:
[SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 0
With this change:
[SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iee2523876a8045e70effd5824afc327d1113038b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Fix readouts from the hardware monitor on Fintek F71808A Super I/O.
The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61.
Referred to util/superiotool/winbond.c and the Linux kernel driver f71882fg.
Tested on a HP 500-319na (Memphis-S / IPM87-MP).
Signed-off-by: Ravi Mistry <rvstry@protonmail.com>
Change-Id: I2b2b98c62f9305c6f4885c2ce3b1444801dcb9d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The headers added are generated as per FSP v3361.07
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:254054169
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If486867477c88ad3e2ec5041ef94a0c364f5dfd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Enable x86 SHA accelerator for use by VBOOT library. This is useful when
CBFS verification verifies the hash of the file being loaded in x86.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~10 ms with CBFS verification enabled.
Change-Id: I14efe7be66f28f348330580d2e5733e11603a023
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68954
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently build rules allow using x86 SHA extensions for all coreboot
stages when enabled. On some SoCs where verstage can run in non-x86
environment, x86 SHA extension cannot be used. Update build rules
accordingly such that x86 SHA extensions can be used in AMD SoCs. This
is particularly useful when CBFS verificiation is enabled which verifies
the hash of the CBFS file being loaded.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe that hardware acceleration
is used when a CBFS file is loaded and observe an overall improvement of
10 ms.
Change-Id: I4f388e963eb82990cda41d3880e66ad937334908
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68953
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
