d071c4d3c3
nb/intel/ironlake: Use DMIBAR/EPBAR macros
...
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: Ie0198a44589271de0335a51937e95662db891d98
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-09-22 17:36:14 +00:00
4c0cea2147
mb/system76/lemp9: convert inverted SCI/SMI macros to _LOW macro
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Convert PAD_CFG_GPI_S*I(..., INVERT) to PAD_CFG_GPI_S*I_LOW(...), which
is better understandable.
Change-Id: I147c82d738623bff54122ad5ef8ece028c562cab
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45488
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-09-22 17:35:18 +00:00
2ee83f8df4
cml-u,whl-u: Disable above 4G allocation to fix running out of MTRRs
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Change-Id: Icfee8750ad225e5b4f2fd1118230b7c0b8d0f850
2020-09-22 11:21:38 -06:00
555c3b1d9b
soc/nvidia: Drop unneeded empty lines
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Change-Id: I76430f5cd4b661aff85e2d21722f41c03362b1bd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44598
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-09-22 17:14:59 +00:00
cb795f0ff9
soc/cavium: Drop unneeded empty lines
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Change-Id: I01227e3c5b650f56e81c5c8e724e3768f06f4530
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44597
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-09-22 17:14:49 +00:00
ed098694b0
mb/kontron: Drop unneeded empty lines
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Change-Id: Ie106bbc8222dce60c837042a313d069289c79322
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-22 17:14:38 +00:00
261226dd42
mb/google: Drop unneeded empty lines
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Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-22 17:14:10 +00:00
ca36aedb4e
acpi: Add SSDT pstate helper functions
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Add new generic helper functions for PSS, PCT, XPSS, objects.
BUG=b:155307433
TEST=Boot Morphius and dump SSDT. Confirm PSS and PCT objects appear
as expected and conform to ACPI_6_3_May16.pdf ACPI specification.
Check XPSS against Microsoft "Extended PSS ACPI Method Specification"
XPSS_spec.doc April 2, 2007.
BRANCH=Zork
Change-Id: I1ea218bcee33093481e82390550ff96d9d2cb8b5
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2020-09-22 16:06:34 +00:00
64004943b4
cml-u: Remove unused TBT ACPI code
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Change-Id: Iade0316d76f2bd1fb037fcdb18e7d81f3b6fdbb0
2020-09-22 06:23:05 -06:00
c97a435978
cml-u: Sync devicetree changes from lemp9
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Change-Id: I69855d082708b185815343b2d92807f3028b2478
2020-09-22 06:23:01 -06:00
e13bade2dd
cml-u: Remove hacks no longer required for thunderbolt and camera toggle
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Change-Id: I17e293f524253a14d7a07842f7abf8e75ad472a8
2020-09-22 06:22:55 -06:00
ccbe5307d8
soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFN
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Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.
BRANCH=None
BUG=None
TEST=Built and tested on dedede board
Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-09-22 07:02:26 +00:00
e5655a11d2
src/mainboard: Add missing <console/console.h>
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"post_code()" needs <console/console.h>.
Change-Id: Ice92d5e259b369da949006bf471a0cb249291897
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2020-09-22 07:01:58 +00:00
aca5d18efd
mb/apple/macbook21/acpi: Convert *.asl to ASL 2.0 syntax
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It changes the binary for apple/macbook21 because of optimization of "Store" instruction.
Generated build/dsdt.dsl files are same.
Change-Id: I16b5180f8a8c44e6bc3ef353a99ef92a381b3295
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-09-22 07:01:22 +00:00
18582237ac
src/lib/bootblock.c: make bootblock_main_with_timestamp public
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bootblock_main_with_timestamp function allows to proceed with existing
timestamp table. Apparently we never needed this, but Zork runs verstage
in the PSP before bootblock.
It'd be useful if we can grab timestamps for verstage from PSP and
merge with coreboot timestamps. Making it non-static will enable us to
do that.
BUG=b:154142138, b:159220781
BRANCH=zork
TEST=build firmware for zork
Change-Id: I061c3fbb652c40bafa0a007aa75f2a82680f5e0a
Signed-off-by: Kangheui Won <khwon@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-09-22 07:00:34 +00:00
4e2f5fd141
soc/amd/picasso: record timestamps in psp_verstage
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Verstage in PSP used stub for timestamps since we didn't know about
clock. Now we figured out clock source so we can enable timestamp
functions.
BRANCH=zork
BUG=b:154142138, b:159220781
TEST=build without CONFIG_PSP_VERSTAGE_FILE, flash and boot
Change-Id: I431a243878e265b68783f54ee9424bb1d4fe03c1
Signed-off-by: Kangheui Won <khwon@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-09-22 07:00:22 +00:00
b13bd1efcf
Revert "soc/intel: Refactor do_global_reset() function"
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This reverts commit 77cc3267fcfurquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
2020-09-22 05:13:39 +00:00
5bd4adf542
mb/google/dedede/variants/madoo: Adjust I2Cs CLK to meet spec
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After adjustment on madoo
Touch Pad CLK: 381.9 KHz
Touch Screen CLK: 389.4 KHz
Audio CLK: 380.9 KHz
BUG=b:168565823
BRANCH=master
TEST=USE=build madoo and measure by scope with madoo.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com >
Change-Id: If281f9a8614e3e0ef20893b456f46e68ecb0631d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2020-09-22 05:01:28 +00:00
370b8b6cef
superio/ite: Distinguish between chips for PECI readings
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Some chips can read external temperature sensor values only to TMPIN3.
These use EC register 0x55, bit 7 to enable that. This patch adds
support for this. It is called "old PECI" by lm_sensors [0].
Other chips can read to any TMPIN[1-3] which is configured in EC
register 0x51 like the other temperature sources. This was the only
supported method. This patch adds a Kconfig option to indicate this
variant.
This patch was tested on an Acer Aspire M3800 which has an IT8720F that
reads the CPU temperature via PECI. It allows the automatic fan control
feature of the Super I/O to work.
Overview of support per chip in the coreboot tree, determined from
reading the publicly available datasheets or lm_sensors, if noted:
Old PECI:
* IT8718F
* IT8720F
* IT8781F, IT8782F, IT8783E/F
Normal PECI:
* IT8721F (exception: no PECI to TMPIN2)
* IT8728F
* IT8772E (uses separate code in coreboot, not superio/ite/common)
* IT8786E
* IT8613E, IT8623E (lm_sensors)
[0] Linux kernel 5.4.48, drivers/hwmon/it87.c
Signed-off-by: Michael Büchler <michael.buechler@posteo.net >
Change-Id: Iab7115852437d46c9b1269bba61ffcf680fe5a6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-09-22 01:11:02 +00:00
e4031c558d
mb/system76/lemp9: gpio: convert the remaining raw pads to macros
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Convert the EC and touchpad interrupt pads from raw to macros. This
was done with intelp2m.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Change-Id: I79d2cca0f300e6daf1c1923a1882e4cc1ffc3c8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43648
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-09-21 23:52:21 +00:00
a45e840309
mb/intel/tglrvp: Enable CSE Firmware Lite SKU
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CSE Lite SKU is CSE FW designed for Chrome and this enables CSE Lite SKU
support for tglrvp.
BUG=None
TEST=Build and boot tglrvp with CSE Lite and Consumer SKU
Change-Id: Ia5f3e8125b5e7760a62f7fb46aeeae85c32e2037
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41132
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-09-21 18:58:34 +00:00
dddd1cc691
src/northbridge: Drop unneeded empty lines
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Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-09-21 16:32:10 +00:00
7aa3372ce2
soc/amd: Drop unneeded empty lines
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Change-Id: Ib262955a1d26681c796c4b10d2b336f2715824d0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:30:40 +00:00
690b6bcb49
treewide/Kconfig: Drop unneeded empty lines
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Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:30:14 +00:00
131d9f5190
src/southbridge: Drop unneeded empty lines
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Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:29:35 +00:00
b69bbfe1ef
soc/qualcomm: Drop unneeded empty lines
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Change-Id: If76502ff91896959ef171c192b4fc138dff18fc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:27:16 +00:00
f91bcb310b
src/security: Drop unneeded empty lines
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Change-Id: Icb6057ac73fcc038981ef95a648420ac00b3c106
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:26:17 +00:00
4b7f3151a8
mb/intel: Drop unneeded empty lines
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Change-Id: I3fdc521d30155c4275c336afe03244311f584e71
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44617
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-09-21 16:24:45 +00:00
3ff7bcf10e
payloads: Drop unneeded empty lines
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Change-Id: I6faeb7c783052edc4217d2d301dbb905e1fc6a19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:20:57 +00:00
99e0c7ddc1
src/cpu: Drop unneeded empty lines
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Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:20:30 +00:00
b6265139c7
soc/rockchip: Drop unneeded empty lines
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Change-Id: I6932580a373608d3d2fa5d844efdc7ffbc577d1f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:18:49 +00:00
0c2724c844
soc/samsung: Drop unneeded empty lines
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Change-Id: Ib2843c40de8e4607b8b9d665761a689227878bc0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:18:07 +00:00
0180e43f3d
soc/intel/common: Keep common non-IP code block inside basecode
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Expand the scope of 'common/basecode' directory to keep common
non-IP code block (like acpi, power limit).
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Change-Id: I7a2778704016b501eb20382d4603295cec8375d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45522
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-09-21 16:16:46 +00:00
2854f40668
src/soc/intel: Drop unneeded empty lines
...
Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-09-21 16:15:25 +00:00
ee65079c96
mb/msi: Drop unneeded empty lines
...
Change-Id: Id51da519582856b1856479b641599e14f79fd1ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:06:36 +00:00
5548ce5896
mb/protectli: Drop unneeded empty lines
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Change-Id: I051dc318c5f881bc58b1a4460faad6af22049b39
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:06:13 +00:00
41376c6d1a
mb/scaleway: Drop unneeded empty lines
...
Change-Id: If56031a7b39d1c1b3ebf6d19376f19ec8c7cef1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:05:49 +00:00
d1b2699685
mb/sifive: Drop unneeded empty lines
...
Change-Id: I5274bc7206ba333d06f5defc35fdede540a7148f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:05:04 +00:00
fbc36dc4b0
mb/roda/rk886ex: Drop unneeded empty lines
...
Change-Id: I229d3995983a05cdd7fef1609a65f31b9f8f2969
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:04:18 +00:00
d0e18ff0cb
mb/dell: Drop unneeded empty lines
...
Change-Id: I3d0ca401cf5268962bcd9074f94c37724cc0a836
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:04:03 +00:00
88b9738fa2
mb/supermicro: Drop unneeded empty lines
...
Change-Id: I1aae6c0291ad329c8cc125cd18ba22dfd63d979b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:03:36 +00:00
8f7a2482ae
drivers/intel/fsp2_0: Add CONFIG_FSP_STATUS_GLOBAL_RESET
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Add CONFIG_FSP_STATUS_GLOBAL_RESET Kconfig to get correct FSP global
reset type from respective SoC Kconfig.
Supported value: 0x40000003-0x40000008, These are defined in FSP EAS
v2.0 section 11.2.2 - OEM Status Code
Unsupported value: 0xFFFFFFFF
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Change-Id: Idc04eb3a931d2d353808d02e62bd436b363600d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-09-21 16:03:28 +00:00
77cc3267fc
soc/intel: Refactor do_global_reset() function
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List of changes:
1. Rename do_global_reset() to force_global_reset()
2. Make force_global_reset() function static
3. Implement force_global_reset() into common/reset.c to avoid
dedicated SoC implementation
4. Remove redundant force_global_reset() implementation from
dedicated SoC
5. Make direct call to global_reset() from cse_lite.c
7. Drop CONFIG_HAVE_CF9_RESET_PREPARE Kconfig from APL SoC due
to common reset (soc/intel/common/reset.c) code migration
8. Remove unused function send_global_reset() from SKL me.c due
to common reset code migration
9. Delete heci.c from APL SoC as unused
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Change-Id: I1c5dc8d5606ef28ffaed4a64d90f470ae1ffc2a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-09-21 16:03:16 +00:00
e49ce2604f
mb/asus/am1i-a: Drop unneeded empty lines
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Change-Id: Ib56b56c05df154522172bff2e6746280286a481f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:03:01 +00:00
7df9cd5ee2
mb/hp/z220_sff_workstation: Add empty lines after "SPDX"
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Change-Id: Ief8df9ef0d6ecb675680aa5120738f5099034139
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45245
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-09-21 16:02:14 +00:00
2fa5c020a4
mb/gizmosphere: Drop unneeded empty lines
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Change-Id: If631055dffa79e7562d6238f6e0b88ad1c7d38b4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:01:47 +00:00
4865983a70
mb/jetway: Drop unneeded empty lines
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Change-Id: Id9837eda69d725539a82b3c98f63a57240051c5b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:01:23 +00:00
fc15ca44f4
mb/elmex: Drop unneeded empty lines
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Change-Id: I6dc9f153270fe501d53ab44c902401893aacf1b9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:00:57 +00:00
c2423e498d
mb/pcengines: Drop unneeded empty lines
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Change-Id: Ica6a885721b3a88814973d1cf086d2d4bc3d922d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 16:00:15 +00:00
d32b44645f
mb/asrock: Drop unneeded empty lines
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Change-Id: I035b66e749e9a3e1bde13c8ed7ceafeb1edbbfa4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2020-09-21 15:59:53 +00:00
