Use USB2_PORT_MID instead of USB2_PORT_TYPE_C, as was done for addw3.
Change-Id: I7df2bbf1ba70c4e08319b760b2784e15c880a105
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This patch updates PMC API name from `pmc_send_pci_enum_done` to
`pmc_send_bios_reset_pci_enum_done` to inform PMC IPC about BIOS done
is also set along with PMC enumeration being done.
BUG=b:270942083
TEST=Able to build and boot google/rex.
Change-Id: I1cf8cb1ecadeb68c109be6b0e751a3f2c448ae4f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH
uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8
P2SB device is being hidden from coreboot by FSP-S. This breaks the
resource allocator which does not report P2SB BAR via intel common
block P2SB driver. Hook up the common block P2SB driver ops to
soc_enable function so that the resources will be reported. The P2SB
device must be set as hidden in the devicetree.
This fixes the silent resource allocation conflicts on machines with
devices having big BARs which accidentally overlapped P2SB BAR.
TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big
BARs and see resource conflicts no longer occur.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7c59441268676a8aab075abbc036e651b9426057
Set the P2SB device as hidden as FSP-S is hiding the PCI configuration
space from coreboot on Alder Lake systems.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d
Fixes the SLB 9672 FW15 failing to stop/resume on S3.
Change-Id: Icb950e02374529547de6d12ee589cde0164d4576
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Declare a child device on the GLAN port so the Ethernet controller is
detected as an onboard device (eno) and not a plugged device (enp).
Change-Id: I43f1b3b749081fd989bb2e5c04f3b616642a5a4f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The power and reset lines from the PCH to the card reader are not
actually connected. Power comes directly from the 3.3V rail, and reset
is controlled by `BUF_PLT_RST#`.
Change-Id: I0a0969e9bcdf1dcf5dfdb512cf329409f187f1b5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
These models were moved to tgl-h. Remove the duplicated files.
Change-Id: If5f719fb162099db340b1f9a1d7a9d29460bc0a3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The serw13 with the 4070 RTX sometimes fails to enumerate the dGPU.
Increasing the delays allows the dGPU to be enumerated consistently. The
values are arbitrary, but still less than the values from proprietary
firmware.
Change-Id: Ibbfda596a324df4b51d583af8d6a36b5cd53a561
Signed-off-by: Tim Crawford <tcrawford@system76.com>
