Currently, having a keyboard connected to the PS/2 controller of the
ASRock E350M1, after suspending and resuming the system, the keyboard
does not work anymore. A similar problem is documented in commit
448e3863 (drivers/pc80: Add PS/2 mouse presence detect) [1].
There is no reason to not disable the controller during resume. Also,
that way, the PS2 ASL method does not need to be overriden.
[1] https://review.coreboot.org/13165
TEST=Resume system, and notice PS/2 keyboard works.
Change-Id: I51dc446861120f80bc9ffc4cc54b86e317d99689
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
These macros, broken since day one, should CreateByteField instead
of CreateWordField. Without the fix, any ASLs that try to use it
will fail to compile with a "ResourceTag smaller than Field"
warning.
Change-Id: Ieeb509aece8836785998b23fdc805a747d40a77a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Instead of setting "peci_tmpin" in the devicetree, THERMAL_PECI is now
a mode of TMPIN like THERMAL_RESISTOR and THERMAL_DIODE. Since the logic
to set temperature offsets and limits is in the function that sets
thermal modes, it makes sense to treat PECI as yet another mode.
As of this commit, there are no boards that actually use peci_tmpin from
ite/common. There are three boards that have a similar device tree
option, but those boards use it8772f, which implements all superio
functions on its own.
The first user will probably be Gigabyte GA-Z77-DS3H.
Change-Id: I39da50c124ad767f8681302733cf004622975e81
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/22076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add devicetree options to set temperature limits that are used to alarm
user when temperature exceeds defined values.
Audio alerts by superio are not implemented yet, but since limits are
visible to userland, some software might use them as is. For instance,
lm-sensors displays "ALERT" when temperature exceeds limits.
Change-Id: I56e041fb78f518d6a9640dc2b3985459991242b9
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a devicetree option to set temperature adjustment registers
required for thermal diode sensors and PECI. However, this commit does
not have the code needed to make PECI interface actually use these
registers. It only applies to diodes.
As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin
to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3".
PECI, apparently, takes precedence over diode, so the adjustment register
will be set and PECI activated. Or simply use the followup patch, which
makes THERMAL_PECI a mode like THERMAL_DIODE.
I don't have hardware to test THERMAL_DIODE mode, but in case of PECI,
without this patch I had about -60°C on idle. Now, with offset 97,
which was taken from vendor bios, PECI readings became reasonable 35°C.
TEST=Set a temperature offset, then ensure that the value you set is
reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset
Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Once w83627hf_set_clksel_48() is unified into
winbond/common/early_init.c by /c/21331 (Unify w*_set_clksel_48()),
this file is no longer needed and can be dropped.
Build tested on select affected mainboards.
Change-Id: I6a5e27fdd48c6e002c3a39dc92fef77e85aea209
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This function is identical throughout all Winbond superios in
the tree, so move it into superio/winbond/common/early_init.c,
renamed from early_serial.c because it now does more than just
early serial.
Change all affected mainboards to use the unified function.
Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Early serial for W83627[HF|EHG] superios are handled by
superio/winbond/common/early_serial.c. Remove code
thus deprecated.
Build tested on select affected mainboards.
Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The 'set' field was not used anywhere. Replace the struct with a simple
integer representing the mask.
initializer updates performed with:
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \
src/ec/*/*/ec.c
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \
src/ec/*/*/ec_lpc.c \
src/superio/*/*/superio.c \
src/superio/smsc/fdc37n972/fdc37n972.c \
src/superio/smsc/sio10n268/sio10n268.c \
src/superio/via/vt1211/vt1211.c
src/ec/kontron/it8516e/ec.c was manually updated. The previous value for
IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and
had a zero bit in the middle of the mask.
Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This device is extremely similar to the IT8718F, so support is based on
existing support for the IT8718F. The CIR device is only detected by
Linux/Windows from the ACPI tables, so ACPI support is extended from the
IT8783E/F (for ACPI). This Super I/O is used on the Foxconn G41S-K.
Tested, working:
* Serial port 1
* Environment controller
- Temperature monitoring
- Voltage monitoring
- Fan control (automatic and manual)
* PS/2 keyboard and mouse
Appears, OS driver loads, but otherwise untested:
* Serial port 2
* Consumer IR
Untested:
* Floppy controller
* Parallel port
* GPIO
Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This replaces the custom environment controller handling in the it8728
driver with the common library.
It also updates the two existing boards with hwm register settings in
their devicetree config so they better match their vendor BIOS fan
control settings.
Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/19293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Current ACPI code for UARTs uses the PNP_DEFAULT_PSC macro for _PSC
(current power state) methods. Override it to `Return (0)` (i.e. cur-
rent state is D0) as the IT8783E/F doesn't have power management.
Change-Id: I3c858dde287dbf7e5fc0c20abb1fd374887acdde
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17791
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This will be used by new Roda boards. Four UARTs and PS/2 keyboard and
mouse are exposed to ACPI. Since our boards only use the environment
controller part, most of the usual pnp interfaces are untested.
Change-Id: Ifeb0327ad115759411716f82585ace5ce55b8464
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17287
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
ITE super-i/o chips need a fourth byte and have a special register
to exit config mode.
Change-Id: Ic40873649d567b87d3a937f2bf068649e67715de
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The devicetree parameter already existed without being
used in the code.
Change-Id: I99dd8bc7a9b2f3509a115a130062d462a62e33fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17614
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the
interrupt is unmapped at reset, but for whatever reason the chip is
inaccessible in smscsuperio/superio.c::enable_dev() and thus the
devicetree.cb IRQ information is not applied in ramstage and then
serial console output fails to work for more than the UART FIFO depth
in the OS.
Change-Id: I00998088975569516f7caeb7f4098b48fe437889
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/10807
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The environment-controller entity is shared by many ITE super-i/o
chips. There are some differences between the chips, though. To cover
that, the super-i/o chip should select Kconfig options of this driver
accordingly.
The current implementation isn't exhaustive: It covers only those
parts that are connected on boards I could test, plus those that are
currently used by the IT8772F. The latter could be ported to use this
driver if somebody minds to test it.
Change-Id: I7a40f677f667d103ce1d09a3e468915729067803
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17284
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Revert commit 53552cc0 (Drop SuperIO nuvoton/nct6776),
removing the code as no other mainboard uses it.
The board Intel Saddle Brook uses this device, so add the
code back with minor adaptations.
Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/16519
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This moves the Kconfig from the Super I/O manufacturer folder
to the chip folder instead.
This makes new chip commits self-contained unit as
edits to the central Kconfig file are no longer required.
Change-Id: I7aee07919f2ae9204850c669e0ed3cb17d4de8cd
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15973
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
This adds support for Nuvoton NCT6791D Super I/O chips.
Makes use of the common Nuvoton early_serial.c.
Based on the Datasheet supplied by Nuvoton.
Datasheet Version: January 8th, 2016 Revision 1.11
Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15967
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Certain mainboards require SuperIO pinmux configuration before
peripherals will become operational. Allow each mainboard to
configure the pinmux(es) of Winbond chips if needed.
Change-Id: Ice19f8d8514b66b15920a5b893700d636ed75cec
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/14960
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The way this was implemented before was causing ACPI failures. There
was also a basic misunderstanding of what the AddressMax field was used
for. In this case, because it's a fixed address, it should be the same
as the AddressMin field.
Getting rid of the addition in the field solves the ACPI output problem.
Change-Id: Idec2bf0ed27ae694e98f141087cdf22401937178
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
The official spelling of Nuvoton is not all uppercase. Only the first
letter is uppercase. See the footer of the Nuvoton Web site.
Change-Id: I6ccd4194d7be0c89f8b332fcca5feb2420a4de1e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/5928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
