Create the banshee variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:214871796
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_BANSHEE
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ib4f943a109f945204a9b0a8de9b99580bf01c87e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
llvm-ar does not support "open" script command, and fails with an error.
This patch fixes it by removing lines `$(AR) rc <object-files>` and
it puts them as "addmod" commands. This way all object files and
archives can be packed into one archive.
Change-Id: I0c53d1d613b5edc321e268d1d996fac3146680f8
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
set_cpu_type(): It determines the CPU type (big or small) that
is executing the function, and marks the global_cpu_type's array slot
which is corresponds to the executing CPU's index if the CPU type is
big core.
get_cpu_index(): It determines the index from LAPIC Ids. This is
required to expose CPPC3 package in ascending order of CPUs' LAPIC ids.
So, the function returns CPU's position from the ascending order list
of LAPIC ids.
TEST=Tested CPU index calculation, core type determination on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch implements a SoC overrides to check CPU privilege level
as the MSR is not consistent across platforms.
For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR
0x151.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch creates a `relative increment by 1` macro to let SoC
gpio pad configuration to be more flexible while adding support
for newer PCH SoC.
With this changes adding GPIO controller support for PCH-N would
become really simple without too much of code duplication.
For example: ADL-N has added `GPP_I` pins into community 1 hence,
the additional code for `PCH-N` whould appear incremetal to ADL-P.
> #define GPP_B 0x0
> #define GPP_T INC(GPP_B)
> #define GPP_A INC(GPP_T)
> #define GPP_R INC(GPP_A)
> #define GPD INC(GPP_R)
> #define GPP_S INC(GPD)
> if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
> #define GPP_I INC(GPP_S)
> #define GPP_H INC(GPP_I)
> #else
> #define GPP_H INC(GPP_S)
> #endif
> #define GPP_D INC(GPP_H)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie3b2183381b877da0a6e5a27f5176f0e21e0c9fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This adds the following commits:
* 22ce1b5 cezanne: Upgrade SMU to 64.60.0
* dd37ad2 cezanne: Update ABL to 0x1B096070
* 01fbf5d cezanne: Update SMU to 64.58.0
* f638765 cezanne: Update ABLs to 0x1A296070
BUG=none
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8f51cb007ce4127428b7b81095fb2c7afb33e608
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO
can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH:
in RW).
BRANCH=None
BUG=None
TEST=Issue manual recovery and confirm DUT is entering recovery mode.
Change-Id: Ib8b6be9fcda24bd2bb479b5b6c01f24a6e9c7b1f
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
The patch moves the CPPC_PACKAGE_NAME macro definition from file
acpi/acpigen.c to include/acpi/acpigen.h file since the
CPPC_PACKAGE_NAME method will get called from cpu/intel/common
in a later patch.
TEST=Built the code for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
That vendor firmware still works after applying `me_cleaner` doesn't
mean that coreboot will also work with the same broken ME firmware.
Instead, one should first test coreboot with the original, unmodified ME
firmware to make sure coreboot works properly, and only then consider
using `me_cleaner` with coreboot. Otherwise, one would end up with a
non-booting or otherwise misbehaving system when trying to use coreboot
and `me_cleaner` without having tested coreboot with the original ME
firmware beforehand, which is hard to diagnose as the problem may only
happen when the ME isn't running normally.
Change-Id: I1626d747a99969faf7db37c10cf7d87e3977744a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Updating from commit id 4c21b57eb:
2021-07-19 11:36:07 +0000 - (pd: Fix missing polarity_rm_dts in some conditions)
to commit id e486b388a:
2022-01-12 21:11:11 +0000 - (zephyr: Update power policy for API change)
This brings in 2212 new commits.
Signed-off-by: zhixingma <zhixing.ma@intel.com>
Change-Id: I4437f09c3193ec7c89f7f9550940a0fa5464a511
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Thejaswani Putta <theja427@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Turns out 150ms isn't enough in the worst reset conditions. On guybrush
the TPM is reset in S0i3 and the CR50 is allowed to hibernate. The CR50
is woken up and initialized early during S0i3 resume. Occasionally the
CR50 isn't ready before the probe times out.
BUG=b:213828947
BRANCH=None
TEST=suspend_stress_test -c 1000
Change-Id: Ifda438080cf1ad2796c7061223a6a97b8e6e9987
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
FSP 2.3 specification introduces following changes:
1. FSP_INFO_HEADER changes
Updated SpecVersion from 0x22 to 0x23
Updated HeaderRevision from 5 to 6
Added ExtendedImageRevision
FSP_INFO_HEADER length changed to 0x50
2. Added FSP_NON_VOLATILE_STORAGE_HOB2
Following changes are implemented in the patch to support FSP 2.3:
- Add Kconfig option
- Update FSP build binary version info based on ExtendedImageRevision
field in header
- New NV HOB related changes will be pushed as part of another patch
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU
PCIe UPDs), we need to set cpu pcie rp flags in devicetree now.
This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in
all intel projects or system will be blocked at PKGC2R with root port
LTR not enable.
BUG=b:214009181
TEST=Build and DUT (Kano) can enter deeper PKGC state normally.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When using the default initial core display clock frequency (648MHz),
Jasper Lake board might have a rare stability issue where the startup
of Chrome OS in secure mode may hang during re-initializing display in
kernel graphic driver.
Bugzzy didn't show this problem so far, but Intel recommends slowing
the initial core display clock frequency down to 172.8 MHz to prevent
this potential problem.
Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0
(172.8 MHz) for bugzzy.
BUG=None
BRANCH=dedede
TEST=Build firmware and check the DUTs can boot up in secure mode well.
Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake
and ensures disable_heci1() is guarded against this config.
Also, makes dt CSE PCI device `on` by default.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This reverts commit bcd7873ea8.
Reason for revert: It makes beadrix can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants.
================ error log ================
...
Starting depthcharge on Beadrix...
src/vboot/util/flag.c:50 flag_install(): Gpio already set up for flag 5.
===========================================
BUG=b:204882915
BRANCH=None
TEST=Build and boot into OS.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Id5e76fc78a56d30caf9f805a8a430f176a653bbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60849
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pre-bootblock stages (i.e., VBOOT_STARTS_BEFORE_BOOTBLOCK) might not
have the ability to log to the UART, so their console messages are
inaccessible until the boot processes gets into the payload or OS.
This makes it difficult to debug verstage.
This feature will dump the pre-bootblock CBMEM console immediately
after the bootblock console is initialized. I chose to do this in
console_init instead of bootblock_soc_init because I wanted to have the
pre-bootblock contents dumped before the coreboot bootblock starting
message is printed.
BUG=b:213828947
TEST=Boot guybrush with PSP verstage and verify verstage logs are dumped
to the UART.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I363c93ef3ee6c5c303a6a68f88a622e2aa62594c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61012
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function is similar to cbmem_dump_console_to_uart except it uses
the normally configured consoles. A console_paused flag was added to
prevent the cbmem console from writing to itself.
BUG=b:213828947
TEST=Boot guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3fe0f666e2e15c88b4568377923ad447c3ecf27e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The existing Sideband access is with the PCH P2SB. There will be future
platforms which access the TCSS registers through SBI other than the PCH
P2SB. This change abstracts the SBI with common API.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia6201762fe92801ce6b4ed97d0eac23ac71ccd37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Each time the spinlock is acquired a byte is decreased and then the
sign of the byte is checked. If there are more than 128 cores the sign
check will overflow. An easy fix is to increase the word size of the
spinlock acquiring and releasing.
TEST: See that serialized SMM relocation is still serialized on
systems with >128 cores.
Change-Id: I76afaa60669335090743d99381280e74aa9fb5b1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60539
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New CBFS API uses commonlib/bsd/cbfs_serialized.h, which includes
vboot's vb2_sha.h. And, because vboot's includes are not available
in libpayload's installation directory nor in lpgcc paths, it was
causing compilation errors. This patch fixes this issue.
lpgcc will look for `vboot` directory like it is doing for `include`
directory to create correct paths. However, if payload will be built
using libpayload's build dir as a base, then vboot headers from
3rdparty/vboot will be used, as there is no way to pass VBOOT_SOURCE
from makefile to lpgcc.
Moreover, this patch moves VBOOT_SOURCE to the main Makefile to
make it available for installation target, to install headers from
vboot directory provided by caller.
Change-Id: I68dd7e1545cfcaf24547d8a9fe289447c79da222
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reported-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This also uncouples cbfstool from being overly Chromium
specific. However the main objective is to not subprocess
flashrom any more and instead use the programmatic API.
BUG=b:207808292
TEST=built and ran `elogtool (list|clear|add 0x16 C0FFEE)`.
Change-Id: I79df2934b9b0492a554a4fecdd533a0abe1df231
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
