876cffae65
Update vboot submodule to upstream master
...
Updating from commit id 13f601fb:
2021-09-24 12:25:24 +0000 - (vboot: boot from miniOS recovery kernels on
disk)
to commit id 25b94935:
2021-12-29 21:34:41 +0000 - (vboot_ref/futility: Wrap flashrom_drv
behind USE_FLASHROM)
This brings in 44 new commits.
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org >
Change-Id: Ife75d21ddfa0b956fdf7a638cd53b55b11f6cb7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2022-01-04 06:49:49 +00:00
1106bcce0d
mb/google/dedede/var/bugzzy: Initialize display signals on user mode
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Bugzzy uses panel-built-in touch screen, it needs to set panel power
and reset signal to high for touch screen to work.
On user mode, coreboot doesn't initialize graphics since there is no
screen display before OS. So we would add a WA to initialize required
signals on user mode. It takes under 30 ms delay on booting time.
BUG=b:205496327
BRANCH=dedede
TEST=Verified touch screen worked with test coreboot
and test touch screen 028D firmware
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com >
Change-Id: Iaa4d16deb932f43ae1ab33ff5b4e74120ab670db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-01-03 21:15:07 +00:00
2a4858afed
mb/google/brya/var/brask: Change I2C/DDC signals
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The latest schematics changes the EN_PP3300_SSD from GPP_D11 to GPP_F14,
I2C/DDC signals from GPP_E22/E23 to GPP_D11/D12.
BUG=b:206602609
TEST=build pass
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com >
Change-Id: I1e4aa6c540806c34b4a642f7813de0a64c6ea2b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Zhuohao Lee <zhuohao@google.com >
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com >
2022-01-03 16:15:39 +00:00
69107c149b
drivers/intel/fsp: Map FSP debug level to coreboot console level
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This patch maps coreboot console level to FSP debug level. This
is useful to suppress MRC (FSP-M) debug logs.
Callers have to select HAVE_DEBUG_RAM_SETUP config to get verbose MRC
debug log,
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I398d576fad68a0d0fc931c175bbc04fcbc2e54ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-01-03 15:07:26 +00:00
b4a169a1e1
soc/intel/alderlake: Add option to make MRC log silent
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Typically, FSP-M aka MRC debug log level defaults to `3`
meaning prints all `Load, Error, Warnings & Info` messages.
Sometimes it's too much information to parse even when users
aren't required to have such detailed information hence,
implement `fsp_map_console_log_level()` that maps coreboot console
log level to FSP-M debug log level and suppress verbose MRC debug
messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and
then the user can enable `DEBUG_RAM_SETUP`.
TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP`
and user to select `DEBUG_RAM_SETUP` config to override
`SerialDebugMrcLevel` UPD value to '5' aka verbose.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2022-01-03 15:07:00 +00:00
627313081e
console: Make get_log_level a public function
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Other drivers may need to know the coreboot log level hence,
export this function rather than marking it static.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I56349f22c71c9db757b2be8eeb2dbfe959f80397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2022-01-03 15:06:52 +00:00
83ef7a647d
mb/google/brya/var/gimble: Update Slow Slew Rate
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- Set slow slew rate VCCIA and VCCGT to 8
BUG=b:206704930
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com >
Change-Id: I1e36c29e82af631cd650d46b67f031d275c97711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: YH Lin <yueherngl@google.com >
2022-01-03 01:36:50 +00:00
355d8444a8
drivers/intel/fsp2_0/notify.c: Group per-phase data
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Group all data specific to each notify phase in a struct to avoid
redundant code.
Change-Id: Ib4ab3d87edfcd5426ce35c168cbb780ade87290e
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2022-01-02 12:34:13 +00:00
654930e7f2
drivers/intel/fsp2_0/notify.c: Clean up some cosmetics
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Sort includes alphabetically, drop spaces after type casts and unbreak
some long lines that are less than 96 characters long.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I2dafd677abbdd892745fea1bf4414f6e0d5549bb
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2022-01-02 12:33:45 +00:00
2b1f8d4129
drivers/intel/fsp2_0: Print return value when dying
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When coreboot goes to die because FSP returned an error, log the return
value in the message printed by `die()` or `die_with_post_code()`.
Change-Id: I6b9ea60534a20429f15132007c1f5770760481af
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2022-01-02 12:33:23 +00:00
346bb0b010
soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode
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Since TGL `spi_protection_mode` bit replaces the previous
`manufacturing mode` without changing the offset and purpose
of this bit.
This patch renames to `manufacturing mode` aka `mfg_mode` to
maintain the parity with other PCHs as part of IA-common code.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I6d00f72ce7b3951120778733066c351986ccf343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
2022-01-02 12:29:07 +00:00
e065db0dc2
soc/intel/common/blk/crashlog: Drop some new lines
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Remove unnecessary new lines in crashlog code.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I0920f563d6fdf9414eab86796cedcac83173dba3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-02 12:17:50 +00:00
f424c8b80f
soc/intel/tigerlake/fsp_params.c: Use is_dev_enabled()
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Change-Id: I3e79f637bedec0bdca1312291328b2385bd027a7
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
2022-01-01 22:24:31 +00:00
b6519812d4
pci_device.c: Don't guard pci_dev_disable_bus_master()
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The `pci_dev_disable_bus_master()` function doesn't need to be guarded
with `CONFIG(PC80_SYSTEM)`, so move it out of the guard.
Change-Id: I813e0f72c3c624c73ab9ecbe7512359608ace927
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2022-01-01 19:17:08 +00:00
434fd4cbc1
mb/google/rambi: Select board-specific options per board
...
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I20d79d4b42908314dbf7021a67b92e5fd2b79556
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 18:03:25 +00:00
9e8f8c18c1
mb/google/volteer: Move selects from Kconfig.name to Kconfig
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Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I72c0e0c3968cb2e92b35381691762148f4c270e4
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 17:57:47 +00:00
d6b181f81c
mb/google/deltaur: Select board-specific options per board
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Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I71f22100fe56a8b88321d220f98ac03887ce6bd7
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 17:57:24 +00:00
df2bb60560
mb/google/deltaur: Move selects from Kconfig.name to Kconfig
...
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I9b523ebee2d2af8585736588306ca687dfe16003
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 17:57:11 +00:00
1aa197ee9b
mb/google/cyan: Move selects from Kconfig.name to Kconfig
...
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ifcdfd9fff197391ca0da083e7f6151c2dffe3374
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 17:56:56 +00:00
a4320fcc7b
mb/google/auron: Select board-specific options per board
...
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I5c437ee2d62415f9048a24ad4a517fc33eec3cf1
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60360
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-01-01 17:56:29 +00:00
338bd0bcf4
mb/google/auron: Move selects from Kconfig.name to Kconfig
...
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ic9e001721baa7b7df89204eed03375e872c93e28
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 17:56:07 +00:00
bbe6e9706a
mb/google/beltino: Move selects from Kconfig.name to Kconfig
...
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Id1bbe7d68d9eace3f54e9decbd02f8b2b50d6867
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 17:55:56 +00:00
1c5e9d1331
mb/google/jecht: Move selects from Kconfig.name to Kconfig
...
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ieb6626aeb2023ac27eac8a515cc0e561607f9f62
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 17:55:48 +00:00
35f903074d
mb/google/slippy: Select board-specific options per board
...
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I1cfea0491f707052db2fbcee078e2c27c5a306c5
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 17:55:39 +00:00
8973942adf
mb/google/slippy: Move selects from Kconfig.name to Kconfig
...
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I677770168caa95d95fd7d32cadc15ffae8455e8c
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 17:55:29 +00:00
0a0a890d3b
mb/google/rambi: Move selects from Kconfig.name to Kconfig
...
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ibd78e1c42d6184127277c1b5dea66150027444fe
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2022-01-01 17:54:25 +00:00
b7ec42d2ff
src: Use 'stdint.h' when appropriate
...
Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-01 14:58:44 +00:00
8292f4160a
src: Remove duplicated includes
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Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2022-01-01 14:56:42 +00:00
b23571c18e
src: Drop duplicated includes
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<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>,
<stdbool.h>, <stdint.h> and <stddef.h> headers.
Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2022-01-01 14:55:51 +00:00
fe657614e9
vendorcode/intel/fsp/elkhartlake: Drop obsolete headers
...
Elkhart Lake was hooked up to the FSP repo with commit 79fcadb3c4felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
2022-01-01 14:28:10 +00:00
6af4200523
mb/google/jecht/acpi: Replace LNot() with ASL 2.0 syntax
...
Replace `LNot (a)` with `!a`.
Change-Id: I4a9165b4610d7d035509b7f10eed0d9847afca1f
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:26:08 +00:00
e81d12e866
ec/smsc/mec1308/acpi: Replace LNot() with ASL 2.0 syntax
...
Replace `LNot (a)` with `!a`.
Change-Id: I16e30f4a774c8ffca3bdbbf57c9a0c6f6d3ca72c
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:25:54 +00:00
1a6925cd7c
superio/winbond/w83627hf/acpi: Replace LNot() with ASL 2.0 syntax
...
Replace `LNot (a)` with `!a`.
Change-Id: I9f08cc180614e7d966256b2944745b0bc1d29865
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:25:39 +00:00
ecc63d9bf4
ec/quanta/it8518/acpi: Replace LNot() with ASL 2.0 syntax
...
Replace `LNot (a)` with `!a`.
Change-Id: I98ac7a9c1cd16609cf6bd38e1bd9bf8cf54817fb
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:25:27 +00:00
9dafc29cae
ec/lenovo/h8/acpi: Replace LNot() with ASL 2.0 syntax
...
Replace `LNot (a)` with `!a`.
Change-Id: I8de151e7df39a0282d032b8ca96c2d1b01014c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:25:14 +00:00
98be4d6ea5
ec/google/chromeec/acpi: Replace LNot() with ASL 2.0 syntax
...
Replace `LNot (a)` with `!a`.
Change-Id: I2bf5a09df831b66197c2a9af780c873290e12b42
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:25:02 +00:00
d4a91aaf1f
ec/quanta/it8518/acpi: Replace Decrement() with ASL 2.0 syntax
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Replace `Decrement (a)` with `a--`.
Change-Id: Ibf5bdb1b3c2524194089b27a8af61b84f517e117
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:24:51 +00:00
9f8ce8f2eb
ec/quanta/ene_kb3940q/acpi: Replace Decrement() with ASL 2.0 syntax
...
Replace `Decrement (a)` with `a--`.
Change-Id: I2105c22d15d4f078270911a7fa7290b3a9b6b841
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:24:09 +00:00
fa36e65a86
ec/google/chromeec/acpi: Replace Decrement() with ASL 2.0 syntax
...
Replace `Decrement (a)` with `a--`.
Change-Id: Ie2d5856316e2c8faac657c6caf79a46f099353be
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:23:50 +00:00
66e2630052
drivers/intel/gma/acpi: Replace Decrement() with ASL 2.0 syntax
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Replace `Decrement (a)` with `a--`.
Change-Id: I45c3d339652dd457cd4664ed03123eee2d7a5684
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:23:00 +00:00
c104e4cdd7
soc/intel/apollolake/acpi: Replace Decrement() with ASL 2.0 syntax
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Replace `Decrement (a)` with `a--`.
Change-Id: I523c6b14c127ec7c0eb41078fb2eb92f42d74bd5
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:22:39 +00:00
40bc82fcde
sb/intel/i82371eb/acpi: Replace Decrement() with ASL 2.0 syntax
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Replace `Decrement (a)` with `a--`.
Change-Id: Iae59333a910cc913bb28ed5436c124b2ab282435
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60587
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-01-01 14:22:30 +00:00
e15e64054c
mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
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When using the default initial core display clock frequency, Magolor has
a rare stability issue where the startup of Chrome OS in secure mode may
hang. Slowing the initial core display clock frequency down to 172.8 MHz
as per Intel recommendation avoids this problem.
Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0
(172.8 MHz) for magolor.
BUG=b:206557434
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-01 14:20:27 +00:00
355fb2fb98
soc/intel/jasperlake: Add CdClock frequency config
...
Add a devicetree setting to configure the CdClock (Core Display Clock)
frequency through a FSP UPD. Because the value for this UPD's default
setting is non-zero and devicetree settings default to 0 if not set,
adapt the devicetree values so that the value for the UPD's default
setting is used when the devicetree setting is zero.
Also update the comment describing the FSP UPD in the header file
FspsUpd.h to match the correct CdClock definition.
BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang@intel.com >
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-01 14:19:53 +00:00
e7f1f6be86
mb/aopen/dxplplusu/acpi: Replace Decrement() with ASL 2.0 syntax
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Replace `Decrement (a)` with `a--`.
Change-Id: I4320d86ce91e7070dc10fcefff6cbc0956be9788
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60586
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-01-01 14:12:59 +00:00
da4c4ded58
mb/aopen/dxplplusu/acpi: Replace Increment() with ASL 2.0 syntax
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Replace `Increment(a)` with `a++`.
Change-Id: I52315e71a51de5c85f11d68854dfe68a474d5cbe
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:10:50 +00:00
70f59e28a0
ec/quanta/ene_kb3940q/acpi: Replace Increment() with ASL 2.0 syntax
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Replace `Increment(a)` with `a++`.
Change-Id: Ic009a868e98cc23dff16154244d65080c1edfa22
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:09:48 +00:00
176279eff1
ec/quanta/it8518/acpi: Replace Increment() with ASL 2.0 syntax
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Replace `Increment(a)` with `a++`.
Change-Id: I5de24042a1a69975c980f6ef10babf6f478b8d69
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:09:36 +00:00
0e790c6cba
ec/smsc/mec1308/acpi: Replace Increment() with ASL 2.0 syntax
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Replace `Increment(a)` with `a++`.
Change-Id: Ib2154767cfc547ca9bd0a23937d50689be13fbcf
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:09:24 +00:00
c8c312c7e8
soc/intel/apollolake/acpi: Replace Increment() with ASL 2.0 syntax
...
Replace `Increment(a)` with `a++`.
Change-Id: I40d5df41e2e077cb9d3e7f3945f0dbae18382a28
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-01 14:09:14 +00:00
