This prevents a headscratcher when .config in root doesn't have a write
permission bit set which causes a build failure of savedefconfig
not able to write to copied file, for example
*** Error while saving defconfig to:
build/mainboard/emulation/qemu-i440fx/cbfs-file.eU5E0t.out.tmp2
Change-Id: I2e7d35c9f6e8add3e7438d163850bc5fda5a99b2
Signed-off-by: Richard Marko <srk@48.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.
TEST=build/boot Win11 on google/brya (kano), verify FPR does not show
up as unknown device under Device Manager.
Change-Id: Ie73fd9d448ecca9e9112abc0d92b4ab46ce3618d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.
TEST=build/boot Win11 on google/hatch (jinlon), verify FPR does not
show up as unknown device under Device Manager.
Change-Id: Ia4a908afdabad0ae8db45c4731a00c9cb17b42bb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch allows google/rex mainboard to choose between "Performance"
(PL_PERFORMANCE) and "Baseline" (PL_BASELINE) power limits (PLs).
This is important for platform to meet balance between power and
performance.
The OEM design google/screebo selects baseline power limit to maintain
the balance performance in lower power.
BUG=b:307237761
TEST=Able to build and boot google/screebo.
w/o this patch:
screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL"
[INFO ] CPU PL1 = 15 Watts
[INFO ] CPU PL2 = 57 Watts
[INFO ] CPU PL4 = 114 Watts
w/ this patch:
screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL"
[INFO ] CPU PL1 = 15 Watts
[INFO ] CPU PL2 = 40 Watts
[INFO ] CPU PL4 = 84 Watts
Change-Id: I43debc5442ae9c01851652beba676ffc102ca27d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I2f641ce1fc44a9d7c9f9c403d255997214021f47
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I15f326774850b3c9562f7eebb78f29430dec1031
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78667
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I75aeb46ea3b4a7c0a41dce375735e7b42ed59587
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78664
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I92414efc9ddb849ceb8b9c4f0bc564bdbd92773b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78638
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DDR interfaces emit electromagnetic radiation which can couple
to the antennas of various radios that are integrated in the system,
and cause radio frequency interference (RFI). The DDR Radio Frequency
Interference Mitigation (DDR RFIM) feature is primarily aimed at
resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies
for the Wi-Fi high and ultra-high bands (~5-7 GHz).
This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature
for Craask variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=None
BRANCH=None
TEST=Build and boot Craask.
- Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I5560bbedb26e88edd9d35f16b639fe63ef42c30e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Just as in commit 38569d0610: ("mb/lenovo/{x230, x230s}: Disable
SuperSpeed capabilities for WWAN USB")
Although on ThinkPads with Panther Point PCH the usb port inside wwan
socket is usually wired to XHCI, it has actually no SuperSpeed lines,
so maybe it is okay to disable SuperSpeed capabilities, and wire them
to EHCI #2 by making use of XUSB2PRM and USB3PRM.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I61e61283a821686558f7f3fdfac7073bb3557e93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78680
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Meteor Lake has a UPD config called In-Band ECC(IBECC) which uses a part of the system DRAM to store the ECC information. There are a few UPD parameters in FSP-M to configure this feature as needed.
This patch adds code to expose these parameters to the devicetree so
that they can be configured on the mainboard level as needed.
Change-Id: Ice1ede430d36dff4175a92941ee85cc933fa56d5
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.
While on it, remove superfluous comments related to modified lines.
Change-Id: I27bac17098beb8b6cb3942e68a37da0095f0d0bd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch introduces a dedicated devicetree.cb file for platforms
built with pre-production SoC. This will help to keep the SoC
configuration separate for platforms with ESx and QSx silicons.
For example, the SaGv WP configuration is different between
pre-production (aka ESx) and production (aka QSx) silicon.
BUG=b:306267652
TEST=Able to build and boot google/rex4es.
Change-Id: I01b0abeeb25ce5a83882c56b30929228fcc6c95c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
For variants without a digitizer, disable I2C2.
For variants without a proximity sensor, disable I2C3.
For variants without a fingerprint reader, disable SPI1.
For all variants, disable I2C5 as it is unused.
Adjust comment blocks as needed.
Change-Id: I27e9eb2b0dcc869d1964c0b17c656d6691c0f05e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78553
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.
While on it, remove superfluous comments related to modified lines.
Change-Id: I769233a5baabbea920c9085f8008071ba34bb9dd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78598
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
