Commit Graph

28012 Commits

Author SHA1 Message Date
Jeremy Soller
a8c7e5dc0b Add System76 ACPI device to implement LED support with 2019-03-01 19:35:07 -07:00
Jeremy Soller
0e7f0928f3 Update blobs internal 2019-02-28 11:21:17 -07:00
Jeremy Soller
b29e5075e1 Use Mini DisplayPort by default 2019-02-28 11:11:32 -07:00
Jeremy Soller
5ca32c0855 Update blobs 2019-02-27 14:06:05 -07:00
Jeremy Soller
69ac9be039 Add SMM to all configs 2019-02-27 13:51:31 -07:00
Jeremy Soller
e60b69f461 Add smmstore for EFI variables on galp3-c 2019-02-27 13:40:07 -07:00
Arthur Heymans
d5999adedc drivers/smmstore: Fix some issues
This fixes the following:
- Fix smmstore_read_region to actually read stuff
- Make the API ARCH independent (no dependency on size_t)
- clean up the code a little
- Change the loglevel for non error messages to BIOS_DEBUG

Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
2019-02-27 13:26:43 -07:00
Arthur Heymans
6455edb1b5 sb/intel/common/smihandler: Hook up smmstore
TESTED on Asus P5QC

Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
2019-02-27 13:26:35 -07:00
Jeremy Soller
a80b0ef9a8 Add self flashing script 2019-02-27 13:24:15 -07:00
Jeremy Soller
1842e2a7f4 Quick rebuild script 2019-02-27 13:14:38 -07:00
Jeremy Soller
33ea3e837d Update blobs 2019-02-27 13:08:41 -07:00
Jeremy Soller
1d8832b3ed No longer try to build seabios 2019-02-27 12:57:20 -07:00
Jeremy Soller
5d03264046 UEFI for galp2, galp3, galp3-b 2019-02-27 12:56:14 -07:00
Jeremy Soller
3fab7d1d91 UEFI for darp5 and galp3-c 2019-02-27 12:43:18 -07:00
Jeremy Soller
fc189a3339 Fix UEFI hangs 2019-02-27 12:17:10 -07:00
Jeremy Soller
9e635d2c87 Add grub configuration to make booting different payloads easier 2019-02-26 20:57:03 -07:00
Jeremy Soller
70f3ad9dc5 Update qemu config and blob 2019-02-26 20:19:03 -07:00
Jeremy Soller
1cc43cf180 Update qemu model 2019-02-26 17:33:30 -07:00
Jeremy Soller
d37873beae Update blobs 2019-02-26 12:09:32 -07:00
Jeremy Soller
c3a2c48bf6 soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter
Tested on system76 galp3-c

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: Id346173ac7ae5246de0b38b9dd23be7b72e70f1e
2019-02-26 11:51:19 -07:00
Jeremy Soller
fc7fecf7c8 Revert "soc/intel/cannonlake: Remove DMA support for PTT"
This reverts commit d5018a8f78.
2019-02-26 11:42:26 -07:00
Jeremy Soller
020fb66698 Update blobs 2019-02-26 10:21:56 -07:00
Jeremy Soller
891cc9a939 System76 darp5, galp2, galp3, galp3-b, and galp3-c support 2019-02-26 10:14:03 -07:00
Daisuke Nojiri
7bbed26ca9 ec/google/chromeec: Clarify return value of google_chromeec_command
This patch clarifies the definition of google_chromeec_command.

Currently absence of the definition isn't causing any problem because
wrapper APIs check 'ret != 0' or wrapper APIs check 'ret < 0' for an
interface which returns only negative error codes.

However, there is a chance that a new wrapper API will be addedl which
check 'ret < 0' to catch errors, assuming other interfaces behave the same.
Or existing wrapper APIs will be broken as soon as they're compiled for
another interface.

BUG=chromium:935038
TEST=none

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I2ce7109b5f2a1d5294f167719730bc1f039ba03f
Reviewed-on: https://review.coreboot.org/c/31613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-26 11:19:14 +00:00
YH Lin
967edec254 flapjack: get sku_id from ec (cbi)
On flapjack, retrieve the board information via CBI interface.

Also reserving 0x2 sku_id for the case of un-provisioned board as this is the id
used prior to the readiness of cbi.

BUG=b:123676982
BRANCH=kukui
TEST=provisioned cbi info and verify the sku_id.

Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc
Reviewed-on: https://review.coreboot.org/c/31586
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26 11:18:40 +00:00
Patrick Rudolph
6220f8d833 soc/cavium/cn81xx: Enable RNG for DRAM init
The Cavium DRAM init might use the RNG for pattern generation.
Initialize it before running DRAM init.

Tested on OpenCellular Elgon.
The RNG generates non identical numbers.

Change-Id: I886f920e9941793fb76b56cc5a24a42e23b082e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-26 11:18:18 +00:00
Qii Wang
d569845964 mediatek/mt8183: Modify I2C source clock
This patch change i2c source clock to TOPCKGEN.

BUG=b:80501386
BRANCH=none
TEST=Boot correctly on kukui.

Change-Id: I49e0acda22dba449d0873a95ba5fae79a9cef569
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-02-26 11:15:41 +00:00
Rizwan Qureshi
747154074c soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO
Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC.

Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-26 11:15:05 +00:00
Werner Zeh
db561e6e39 acpi: Sort the reported APIC-IDs in the MADT table
coreboot performs MP-Init in a parallel way. That leads to the fact
that the order, in which the CPUs are woken up, can vary from boot to
boot. The creation of the MADT table just parses the devicetree and
takes the CPUs reported there as it is for creating the single local
APIC entries. Therefore, the OS will see different order of CPUs.
There are CPUs out there (like Apollo Lake for example) which have
shared caches on core-level and if the order is random this can end up
in assigning cores to different tasks or even OSes (in a virtual
environment) which uses the same cache. This in turn will produce
performance penalties across these distributed tasks/OSes.

Though there is a way to discover the core- and cache-topology it will
in the end be necessary to take the APIC-ID into account. To simplify
it, one can achieve the same output by sorting the APIC-IDs in an
ascending order. This will lead to the fact that CPUs that share a given
cache will be reported right next to each other in the MADT.

Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-26 11:14:49 +00:00
Werner Zeh
bd660e2338 commonlib: Add Bubble sort algorithm
Add an implementation for Bubble sort. For now, only integers can be
sorted in an ascending or descending order. It can be later simply
extended to cover other datasets like strings if needed.

The reasons for choosing bubble sort are:
* it is a simple algorithm
* bubble sort is stable, i.e. it does not exchange entries which are not
  needed to be sorted as they are already in order

Change-Id: I2c5e0b5685a907243b58ebe6682078272d316bf6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-26 11:14:41 +00:00
Matt DeVillier
38b6ccfed9 payloads/tianocore: default to MrChromebox's working branch
Rather than attempt to maintain patches against upstream Tianocore, use
MrChromebox's coreboot framebuffer branch as the default build target.

Rework the Makefile to default to MrChromebox's coreboot_fb branch, but
also allow for aribitrary commits from upstream Tianocore to be used
as build targets.

Ensure the branch is synced on each build, as long as working directory
is clean, and that switching between commits or trees is handled sanely.

Eliminate TIANOCORE_MASTER as a selectable build target, since unpatched
it is unlikely to boot on any device. It can easily be specified via
the 'revision' option if desired.

Test: build for the default stable target, for upstream/master
as the specified revision, and for an arbitrary valid commit hash.

Change-Id: I4a83db3cd64c7d5b652c6e95780d10051f143e88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-26 11:13:11 +00:00
Ronak Kanabar
da7ffb48b2 soc/intel/common: Include cometlake PCH IDs
Add cometlake specific PCH IDs

Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-26 02:17:25 +00:00
Philipp Deppenwiese
66f9a09916 security/vboot: Add measured boot mode
* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.

Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 22:29:16 +00:00
Patrick Rudolph
bacd57dfaf cpu/x86/smm: Add qemu's SMM-Revision Level
The SMI handler on qemu returned early, due to missing SMM-Revision
Level support.

Add the ID qemu uses, which is AMD64 compatible for qemu-system-x86_64.

Fixes booting tianocore payload with SMM variable store on qemu.

Change-Id: I978b94150cfc49a39c2a0818eb14a649850e451d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-25 11:21:53 +00:00
Mike Banon
749fe1eef9 src/device/Kconfig: Change default VESA mode from 117h to 118h
Change default VESA/native framebuffer mode (needed for bootsplash and
graphical framebuffer console) from 117h (1024x768 64k-color (5:6:5))
to 118h (1024x768 16.8M-color (8:8:8)) mode.

This provides console output at Lenovo G505S even if e.g. GRUB is the
payload, while it is unlikely to cause any downsides for the other
boards.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ia348199bbd430532b1399706dd84490c9680b5f5
Reviewed-on: https://review.coreboot.org/c/31595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-25 11:21:19 +00:00
Elyes HAOUAS
e2af9b8481 ACPI: Enum only used ACPI tables
enum contained redundant names and wasn't exhaustive anyway.

Change-Id: I4d74ff61c555c5953932efbd7edccfd3157cb5be
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-25 11:20:35 +00:00
Damien Zammit
f0a9128424 intelmetool: Use GPLv2+ where possible
Upstream intelmetool is out of date; I suggest I archive it
instead of trying to merge coreboot's changes into it.

However I would like to preserve the licensing of files in the tool
as GPLv2+ where possible instead of GPLv2-only.

Change-Id: I47b1ff2734f54c65f4214b39244bd868ef44b83c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/31587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-25 11:19:37 +00:00
Patrick Rudolph
b94ecc4e69 soc/cavium/common: Make ecam0_get_bar_val common
Move ecam0_get_bar_val into the common folder and make it public.
Compile it for romstage and ramstage.

To be used by romstage PCI code.
Tested on OpenCellular Elgon.

Change-Id: I18b1ede56795bf8c1f9476592291b8ea610eccd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-25 11:18:32 +00:00
Elyes HAOUAS
99850600d0 sb/amd/hudson/acpi: Fix illegal object references
Issue spotted using IASL 20190215 on mainboard GIZMOSPHERE_GIZMO2:
"Object is created temporarily in another method and cannot be accessed"

Change-Id: I1e4ca2c765083db3a27e415d3a69bef0912a606b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-25 11:17:54 +00:00
Duncan Laurie
a213ed659a ec/google/wilco: Fix ACPI power status events
This change fixes the power status events for AC and battery
events from the EC.  The register that was being used is not
returning the expected information.

BUG=b:125472740
TEST=enable ACPI debug in the kernel and verify that AC and
battery insert/remove are detected properly.

Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-25 11:17:23 +00:00
Kyösti Mälkki
47b9e457fa AGESA vendorcode: Define libagesa rule just once
No reason to keep this rule in per-family directory.

Change-Id: I6bfc9a277674077774c4cb398f8add5e4fa99c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31509
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 11:16:52 +00:00
Kyösti Mälkki
423d03c163 soc/amd/common: Fix AmdLateRunApTask()
Third parameter ConfigPtr of the callout is of type
AP_EXE_PARAMS and needs to be passed back to AGESA
with AmdLateRunApTask() call.

Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/27277
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 11:16:27 +00:00
Werner Zeh
d35a4811db vendorcode/siemens: Cache currently opened hwi file name
On every call of hwilib_find_blocks() the CBFS file will be mapped and
the contents are parsed to get the offsets for every single block. This
is not needed if the CBFS file name is the same for the different calls.

This patch adds a storage for the currently opened CBFS file name in
CAR_GLOBAL and checks on each call if the file to open is already open.
If yes, the file will not be mapped again which saves execution time.

Test=Booted mc_tcu3, mc_bdx1 and mc_apl1 and verified that hwinfo.hex
is only mapped once across several following hwilib_find_blocks() calls.
In addition a test was done to ensure that files with different names
get mapped correctly.

Change-Id: Id69e0f6c914c2b8e4551fd8a4fb7d452d176afb3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-25 05:39:45 +00:00
Patrick Rudolph
87abccdd89 mb/emulation/qemu: Fix fw_cfg file loading
The change bcd84fe "mb/emulation/qemu-i440fx: change file handling"
introduced a regression where it loads only 4 bytes of the
ACPI and SMBIOS table, instead of the whole table.

Load the whole ACPI and SMBIOS table.

Tested on Qemu using GNU/Linux.

Change-Id: Ibacbf7caab9be5f181c12e9dd39a2893b13cf6c9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31593
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 11:57:25 +00:00
Ronak Kanabar
f606a2f5e6 soc/intel/common: Include cometlake SA IDs
Add cometlake specific SA IDs

Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-02-24 04:49:37 +00:00
Ronak Kanabar
128bb2a7ca soc/intel/common: Include cometlake CPU IDs
Add cometlake specific CPU IDs

Change-Id: I75d5b82524c9df1402abf6659d62dbc716c28c30
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-02-24 04:49:25 +00:00
Elyes HAOUAS
d8e55350f1 arch/x86/smbios.c: Remove duplicated 'processor_upgrade'
Change-Id: I3500a648631c91f3a0812c7e661440743ed6a1e1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-23 14:44:18 +00:00
Maulik V Vaghela
3647e5c151 drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO
USE_FSP_REPO used to rely on SOC_INTEL_COMMON_CANNONLAKE_BASE which was
getting selected for cometlake soc also. Since FSP is not yet upstreamed
for cometlake, compilation was failing due to FSP was not found.

So limiting USE_FSP_REPO option to coffeelake and whiskeylake soc only
and excluding for cometlake.

Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-02-23 14:25:31 +00:00
Subrata Banik
ab9f64d011 soc/intel/cannonlake: Make few more whitespace proper in MCH name
CB:31547 fixes few whitespace error. Here is few more whitespace clean up.

Change-Id: I69c12a5da4feb48b2bc23874332ab341a559f6e6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-02-23 04:45:46 +00:00
Kyösti Mälkki
b92853ed56 arch/arm64: Add PCI config support in romstage
Change-Id: I9cc3dc51764f24b986434080f480932dceb8d133
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22 19:32:36 +00:00