Skyrim platforms have I2C3 controller which is shared between PSP and
X86. In order to enable cooperation, PSP acts as an arbitrator. Enable
SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is
binded on the OS side.
BUG=b:241878652
BRANCH=none
TEST=Build kernel and firmware. Run on skyrim and verify TPM
functionality.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I2a3de8cb2b9241e2d81e02df49f317ac0408d5bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The EC_CMD_USB_PD_PORTS host command returns a
struct ec_response_usb_pd_ports, not a
struct ec_response_charge_port_count.
Luckily, both structs have the same memory layout, so this is simply a
name change.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: I0d7710ca8a45f0ea3939f58bbba6bab31ff41919
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69370
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Simplify the implementation of setting the keyboard backlight PWM
value. Host command stubs typcially don't need to examine the host
command's return value as stored in cmd_code because that level of
detail is not very interesting. Higher value error codes are returned in
actual result structures.
This host command can return EC_RES_ERROR for out of range PWM values
which is already a generic error and unlikely to happen since we already
limit the range to 0..100 here. Finally, none of the callers in coreboot
check the return value.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: If17bc4e31baba02ba2f7ae8e7a5cbec7f97688c5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69369
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an ACPI method to handle EC_HOST_EVENT_PANIC (bit 24) events.
EC panic is not covered by the standard (0-F) ACPI notify values.
Arbitrarily choosing B0 notify, which is in the 84-BF device specific
ACPI notify range.
This will be a no-op until the kernel driver is also updated to handle
this event.
BUG=b:258195448
BRANCH=None
TEST=Observe event with modified cros_ec_lpc driver
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Iafa642c1c50f9a0083a8e618e1eabec9a7ce39b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69391
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update SX9324 related settings based on tunned values from the ODM.
This patch supports both legacy and upstream Linux's SX9324 driver.
BUG=b:242662878
TEST=i2cdump -y -f 13 0x28
(Verified register values on Pujjo)
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I34d8073ffe93e6939f8da0cd7efb8667c0e9ac37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69366
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This finds all the boards using a specified Kconfig option and runs both
CrOS and non-CrOS abuilds on them to make sure they're working.
Nobody wants to run the full what-jenkins-does build on their host
machine. Hopefully this can help get some tests run locally before
pushing to coreboot.org.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The deadlock prevention is also needed with CONFIG_X2APIC_RUNTIME when
the cpu is in x2apic mode.
TESTED: Fixes SMI generation on xeon_sp hardware with
CONFIG_X2APIC_RUNTIME.
Change-Id: I6a71204fcff35e11613fc8363ce061b348e73496
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
DTTS is Dynamic Thermal Table Switching Proposal.
DTTS needs one bit to save the body detection result from EC.
Define mode change STTB bit for Desktop (1) and laptop (0).
This bit is Switch thermal table by body detection status.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit eb76a455cd
and applies minor fixes to make it build again.
PARALLEL_MP was working prior to board removal and no
relevant SMI handlers were implemented. So NO_SMM choice
is now selected.
Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the \_SB scope, but those
are defined inside the \_SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.
TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the \_SB scope
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
This code was never tested with SSE enabled. Now qemu enables it and
FX_SAVE encroaches on the save states. Without SSE enabled the handler
just happened to be aligned downwards enough to have the save states
fit. With SSE enabled that's not the case. The proper fix is to give the
code setting up stubs the right base address, which is the same as for
the TSEG codepath.
Change-Id: I45355efb274c6ddd09a6fb57743d2f6a5b53d209
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69233
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
In Linux, the I2C speed defaults to 400 kHz if there is no device
registered in ACPI which requests a different speed. Due to board
limitations (layout, bus load), 400 kHz are too fast which results in a
timing violation. Therefore, add a dummy I2C device to both used I2C
buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus
speed in Linux accordingly.
Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
According to measurements Elkhart Lake seems to drive the internal I2C
controllers with 100 MHz instead of the common 133 MHz. The datasheet
itself is quite vague on this definition, just one place mentions that
it is 100 MHz (register description for offset 0x94).
This patch changes the I2C controller base frequency to 100 MHz. The
verification was done by measuring the set up resulting I2C clock for
both 100 and 400 kHz.
Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
There are SoCs (for instance Intel Elkhart Lake) that do use 100 MHz as
the base clock for I2C controllers. To support them properly add a
frequency setting for 100 MHz to the designware I2C controller driver.
Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
On certain mainboards due to hardware design limitations, certain SPI
Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to
override SPI read modes in boards which do not have hardware
limitations. Currently there is an API to override SPI fast speeds.
Update this API for mainboards to override SPI read mode as well.
BUG=b:225213679
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~25 ms with 100 MHz SPI speeds.
Before:
11:start of bootblock 688,046
14:finished loading romstage 30,865
16:FSP-M finished LZMA decompress (ignore for x86) 91,049
Total Time: 1,972,625
After:
11:start of bootblock 667,642
14:finished loading romstage 29,798
16:FSP-M finished LZMA decompress (ignore for x86) 87,743
Total Time: 1,943,924
Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
SX9324 driver is updated per Linux's documentation found at
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml
Supporting logic for the deprecated SX932x driver is hence guarded by
DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
This patch by itself does not introduce functional changes to any board.
The legacy SX932x Linux driver never reached upstream Linux and is only
available in ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted
a different implementation named SX9324 and has been available since
5.4. Ideally all variants should adopt the new driver; however, during
the transition phase, coreboot must support both drivers. It is better
to have a single firmware build that can work with both Linux kernel
drivers by specifying both sets of properties. Legacy driver support
should be deleted once all variants finish migration.
BUG=b:242662878
TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy
SX932x driver are identical w/ and w/o this patch
(Tested on Craask and Nivviks)
Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69192
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add Fingerprint SPI, and power-off FPMCU during romstage.
For reference see CL:66915 for a similar change to Brya's power sequence
SHA: 2b523ce631 ("Invoke power cycle of
FPMCU on startup")
TEST=Tested on Rex - setup and logged in using fingerprint
Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
