Commit d448f8ce0f (drivers/intel/pmc_mux/
conn: Change usb{23}_port_number fields to device pointers) changed the
way the pmc_mux/conn driver gets the corresponding USB ports from the
devicetree. This change didn't include the corresponding change for the
Taniks and Vell variants of the Google Brya project and the Intel
adlrvp_n_ext_ec board which probably weren't in the tree at the time the
patch referenced above was created. This patch ports the needed change
forward to those boards to fix the build of the upstream tree.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id295cd11fbbfe038534b154215a6de7c1ac13e0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Run the command below to fix all occurrences.
$ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,'
Change-Id: I84669341e2c8976953284dbaf113da3397857de3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Realtek RTL8125 has four registers for four leds
and a feature config register.
We use led0 and led2 in brask, so modify ethernet driver.
Those registers' IO address are based on RTL8125 datasheet.
BUG=b:193750191
TEST=Modify overridetree.cb to verify LEDs' settings.
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add the stylus field in fw_config.
Update devicetree and gpio to handle stylus pen detection.
BUG=b:167983049
TEST=Build firmware and check behavior as following:
1) Set the fw_config "bit4=1" for pen present:
Wake up from suspend when pen is removed from the garage.
Present the stylus menu when pen is removed from the garage.
2) Set the fw_config "bit4=0" for pen absent:
Wake up and present menu will not work when pen is removed
form the garage.
Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60185
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a new port for the ASRock H77 Pro4-M motherboard. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.
The port was initially done with autoport. It is quite similar to the
ASRock B75 Pro3-M which is already supported by coreboot.
Working:
- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
- Native RAM initialization with four DIMMs of two different types
- PS/2 combined port (mouse or keyboard)
- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
- PCIe graphics in the PEG slot
- All three additional PCIe slots
- All rear and internal USB2 ports
- All rear and internal USB3 ports with reasonable transfer rates
- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
- Rear eSATA connector (multiplexed with one ASM1061 port)
- Console output on the serial port of the Super I/O
- SeaBIOS 1.15.0 to boot slackware64
- SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS)
- Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`)
- External flashing with flashrom-1.2 and a Raspberry Pi 1
- S3 suspend/resume from either Linux or Windows 10
Not working:
- Booting from the two SATA ports provided by the ASM1061
- Automatic fan control with the NCT6776D Super I/O
Untested:
- VBT (it is included, though)
- Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
vdd scale: 73457 -> 73331
vdd offset: 291 -> 1893
soc scale: 30761 -> 31955
soc offset: 834 -> 852
BUG=b:207299255
BRANCH=guybrush
TEST=1. emerge-guybrush coreboot
2. pass AMD SDLE/Stardust test
Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
coreinfo and nvramcui are using libpayload/bin/lpgcc and libpayload
build directory as a base, instead of installing it first. This caused
include errors, because commonlib/bsd is not present there. This patch
introduces comonlib/bsd include path to lpgcc CFLAGS if it is being
built using libpayload build directory as a base.
Change-Id: I7d1fe9e5dc3e7c1c1ba825a1bf19972722b42778
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Using Vbt.bin version 244, with the following changes:
* Add 200ms delay to sink (T3) to avoid no response to AUX Channel
transaction, which manifests as a repeating, colourful flicker.
* Increase maximum supported refresh rate to 120Hz
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
2. Hynix H54G46CYRBX267
BUG=b:203837656
BRANCH=dedede
TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI
table), PLD is added to ACPI table. It causes the DUT to not boot into
the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2
to solve this issue.
Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table")
BUG=b:209723556
BRANCH=none
TEST=build coreboot and boot into OS.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60187
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Building an image for the Lenovo T60 with `x86_64-linux-gnu-gcc-11`
fails with the format warning below.
CC ramstage/southbridge/intel/common/rcba_pirq.o
src/southbridge/intel/common/rcba_pirq.c: In function 'intel_acpi_gen_def_acpi_pirq':
src/southbridge/intel/common/rcba_pirq.c:86:69: error: format '%ld' expects argument of type 'long int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
86 | printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n",
| ~~^
| |
| long int
| %d
87 | dev_path(dev), int_pin - PCI_INT_A,
88 | pirq_idx(pin_irq_map[map_count].pic_pirq));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| size_t {aka unsigned int}
The return value of `pirq_idx()` is of type `size_t`, so use the
appropriate length modifier `z`.
Change-Id: I7af24cee536b81e4825b77942bcac75afeb9f476
Found-by: gcc (Debian 11.2.0-13) 11.2.0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently, the pmc_mux/conn driver uses integer fields to store the
USB-2 and USB-3 port numbers from the SoC's point of view. Specifying
these as integers in the devicetree is error-prone, and this
information can instead be represented using pointers to the USB-2 and
USB-3 devices. The port numbers can then be obtained from the paths of
the linked devices, i.e. dev->path.usb.port_id.
Modify the driver to store device pointers instead of integer port
numbers, and update all devicetrees using the driver. These are the
mainboards affected (all are Intel TGL or ADL based):
google/brya
google/volteer
intel/adlrvp
intel/shadowmountain
intel/tglrvp
system76/darp7
system76/galp5
system76/lemp10
Command used to update the devicetrees:
git grep -l "usb._port_number" src/mainboard/ | \
xargs sed -i \
-e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \
-e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g'
BUG=b:208502191
TEST=Build test all affected boards. On brya0, boot device and check
that the ACPI tables generated with and without the change are the same.
Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The Bayhub LV2 has a known errata wherein PCI config registers at
offsets 0x234, 0x238, and 0x24C will only correctly accept writes
when they are addressed via a DWORD (32-bit) wide write operation
on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop
latency register, therefore add a finalize callback to this driver
which will program the LTR max-snoop/no-snoop register with a 32-bit
write using the values from pciexp_get_ltr_max_latencies().
BUG=b:204343849
TEST=verified the PCI config space writes took effect on google/taeko
Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change in power sequencing appears to fix issues with power
consumption of the SD card controller. Possibly this change
ensures the device has enough time to properly initialize itself
after reset is deasserted but before it is accessed.
BUG=b:206014046
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I90e5dd074ceda365283fe7e1f43dfd8c692d7338
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
According to util/kbc1126/README.md, for these ECs to work, the
address and size of their two firmware should be written to $s-0x100`
(`$s` means the image size, done with kbc1126_ec_insert), which means
that every existing section (especially those used to store code)
should not overlap this address, otherwise the bootblock will get
damaged when inserting firmwares of the EC.
In this commit, ecfw_ptr is a structure initialized at build time
according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET
(to do so, they should be redefined as hex), and linked to
CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not
needed at build time any more.
Test passed on Elitebook Folio 9470m.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
