Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will
cause verstage to run during s0i3 resume. The TPM will be reinitialized
in verstage during s0i3 resume. This is necessary on guybrush boards
because the TPM_RST_L pin is asserted by the SOC in S0i3.
BUG=b:200578885
BRANCH=None
TEST=TPM initialized after s0i3
Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Crashlog has error records and PMC reset records two parts. When we
send ipc cmd "PMC_IPC_CMD_ID_CRASHLOG_ON_RESET", PMC reset record is
enabled. At each warm/cold/global reset, crashlog would be triggered.
The cause of this crash would be "TRIGGER_ON_ALL_RESETS", it is used to
catch unknown reset reason. At the same time, we would see [Hardware
Error] in the kernel log.
If we default enable TRIGGER_ON_ALL_RESETS, we would have too many false
alarm. Now we disable PMC reset records part by default. And we could
enable it when we need it for the debug purpose.
The generated bert dump is under /var/spool/crash/, we could check this
path to verify this CONFIG disable/enable status.
BUG=b:202737385
TEST=No new bert dump after a warm reset.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When compiling libpayload using x86_64 toolchain for ARCH_MOCK compiler
reports an error about gerring address of packed member. Until now it
had to be disabled by passing -Wno-address-of-packed-member to
EXTRA_CFLAGS. This patch disables this warning.
Change-Id: I9a948fabe66f7297632ecaca8ec1bfa5c842b750
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
None of the touchscreens used in the brya program (any brya board)
should require exporting of GPIOs in the ACPI _CRS method for any i2c
device. This can cause i2c devices to malfunction or cause timing
sequence violations if:
1) ACPI exports a PowerResource for the device that uses GPIOs that are
also exported in _CRS
2) The kernel driver for the device uses the GPIOs exported in _CRS for
its own purposes. This means the state of the pin is out of sync
between platform firmware and the kernel. The Linux ELAN I2C
touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/input/touchscreen/elants_i2c.c;l=1429)
is one example of this.
Therefore, add disable_gpio_export_in_crs to all brya variants that use
the drivers/i2c/generic or drivers/i2c/hid chip drivers.
Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
We experienced the `Cr50 i2c TPM IRQ timeout!` error when the device
executed the reboot test even though we have updated the Cr50 firmware
to the latest version 0.6.70. Besides, we also experienced the device
failed with the IRQ timeout when using the 0.3.22 Cr50 firmware in the
factory. In order to fix these issues, we disable the gpio power
management from the devicetree.
BUG=b:210540890
TEST=reboot 100 cycles without the error message.
Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Use enum cb_err as return type of all functions that aren't exposed
outside of this compilation unit. The checks if a function has returned
a failure are replaced with checks if the return value isn't CB_SUCCESS
which is equivalent if only those two values are used, but also detects
a failure if any unexpected value would be returned.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
S0i3 is a low power state which reduces the power consumption to about
the level of the S3 suspend state where the DRAM is kept in a self-
refresh state and most of the rest of the system is powered down. So
everything that can be switched off in the S0i3 state should be switched
off in order to maximize the standby time.
BUG=b:210722314
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If445f5825dc7b795c95d73c061156cc485421ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The AOAC device states shouldn't be stored in GNVS, but be read from the
AOAC registers during runtime. Same for the EHCI controller's BAR0. The
location and size of the XHCI firmware can either be statically
determined at build-time or have coreboot generate ACPI objects that
contain the needed addresses. Since I can't easily test changes that
require booting to a desktop on Stoneyridge at the moment, only add
TODOs for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I3691b05606b9430cb60923780a6131993a9887d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Split the southbridge code into a bootblock and a ramstage part to align
it more with Picasso and Cezanne. Also move the implementation of
fch_clk_output_48Mhz to the end of early_fch.c since it's not really
related to the functions that were previously around it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib660fbef8dc25ba0fab803ccd82b3408878d1588
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Split the code that gets called from the AGESA wrapper from the rest of
the FCH/southbridge code that directly interacts with the hardware.
Since the remaining parts of southbridge.c aren't used in romstage,
drop it from the list of build targets for romstage.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6197add0e1396a82545735653110e1e17bf9c303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Introduce and use an enum for the `power_profile` CMOS option. Add a
helper function that converts CMOS values into enum values. Using an
enum allows GCC to warn about switch statements using enum types for
their control expressions not handling all possible enum values, and
also improves readability.
Change-Id: I47a453ea12d164d26908a9944a89a481757e753c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <admin@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We shouldn't be providing -I include paths to the root of the soc
specific directory. It allows for lazy includes that can collide,
but there's no way of knowing the winning path since the winning
path is determined by Makefile.inc parsing order.
This is taken from CB:41355
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45ed219e4e0cccf3d4f04cc70dc1ef77c518afff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Wrap bitfield structs in unions to reduce pointer usage. This adds more
uses of the `mei_dump()` function, only used for debugging. Refactoring
the MEI CSR functions to not use pointers is done in a follow-up.
Change-Id: I4defbb8c0e7812bf95c672ce529959f67c34537a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The RTC on Cezanne is an unstable wake source when the system is in
S0i3. We instead need to use an internal timer that triggers a GPIO that
acts as a wake source. This change provides the ACPI necessary to allow
the OS to manage the wake source.
BUG=b:209705576
TEST=Boot guybrush with this patch and several OS patches. Verified the
OS sets the correct wake bit, the system correctly suspends
and resumes, and the wake source is correctly accounted for.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We want ACPI to own the GPIOs. This will stop the GPIOs from being
exposed to the OS driver.
BUG=b:209705576, b:210694108
TEST=Dump ACPI table and verify GPIO are no longer in _CRS.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d2af41e1d04b98f0e3e19a95d7b91d08ecdf17b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Use the `popcnt()` helper instead of manually counting the number of set
bits in the first `CONFIG_MAX_CPUS` bits with a loop. Also, use unsigned
types to store the number of active/total cores.
Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Setup eSPI to dedicated alert per the latest schematic changes.
DUT won't hang up at power on boot due to eSPI alert is triggerred
unexpectedly.
BUG=b:199458949,b:203446084
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
test power on/reboot on DUT (6 units) each 10 loops->pass
Change-Id: I55cda7a1af22e555a4f55285cb7e337a69e6c234
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
