In cbfs_add_component(), the |offset| variable confusingly jumps back
and forth between host address space and flash address space in some
cases. This patch tries to clean that logic up a bit by converting it
to flash address space very early in the function, and then keeping it
that way afterwards. convert() implementations that need the host
address space value should store it in a different variable to reduce
the risk of confusion. This should also fix a tiny issue where
--gen-attribute might have previously encoded the base address as given
in CBFS -- it probably makes more sense to always have it store a
consistent format (i.e. always flash address).
Also revert the unnecessary check for --base-address in
add_topswap_bootblock() that was added in CB:59877. On closer
inspection, the function actually doesn't use the passed in *offset at
all and uses it purely as an out-parameter. So while our current
Makefile does pass --base-address when adding the bootblock, it actually
has no effect and is redundant for the topswap case.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Idf4721c5b0700789ddb81c1618d740b3e7f486cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:198689479
BRANCH=zork
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59558
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently coreboot and EC had different logic to interpret TCSS port
number which would break retimer update functionality since coreboot
would pass wrong port information to EC.
To correct this, coreboot has implemented function which converts
coreboot physical port mapping to EC's abstract port mapping.
Each SoC needs to implement this weak function since only SoC will have
correct physical port mapping data. This function should resolve issue
of port mismatch since coreboot will count only enabled ports and
provide correct EC port number in return.
BUG=b:207057940
BRANCH=None
TEST=Check if retimer update works on Redrix and correct port
information is passed to EC.
Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently coreboot interprets TCSS port number as per physical port
number while EC abstracts port number and provides indices as port
number. For example, if TCSS port 1 and 3 are enabled on the board,
coreboot will interpret port numbers as 0 and 2, but since only 2 ports
are enabled in the system EC will assign port numbers as 0 and 1.
This creates a port number mismatch while communicating between EC and
coreboot. This patch addresses issue where SoC can implement function
to map correct EC port as per port enabled in mainboard.
BUG=b:207057940
BRANCH=None
TEST=Check if code compiles successfully. Functionality will work once
function is implemented in SoC code.
Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
For additional power savings during RTD3, the PMC can power-gate the
ModPHY lanes that are used by the PCH PCIe root ports. Therefore,
using the previous PCIe RP-type detection functions, implement ModPHY
PG support for the PCH PCIe RPs.
This involves:
1) Adding a mutex so only one power resource accesses the PMC registers
at a time
2) OperationRegions to access the PMC's PG registers
3) Adding ModPHY PG enable sequence to _OFF
4) Adding ModPHY PG disable sequence to _ON
BUG=b:197983574
TEST=50 S0ix suspend/resume cycles on brya0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59855
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Alder Lake. While we're
here, add PCIe RP group definitions for PCH-M chipsets.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7438513e10b7cea8dac678b97a901b710247c188
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Add entry in ACPI table under IPU device to provide silicon type
information to IPU driver. IPU kernel driver can decide the type of
firmware to load based on this information.
BUG=b:207721978
BRANCH=none
TEST=Check for the ACPI entry in the SSDT after booting to kernel
Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f
Cq-Depend: chromium:3319905
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The commit d023909b "treewide: Disable R_AMD64_32S relocation support"
clflush the address stored in _cbmem_top_ptr, which is the same address
cbmem_top() returns, instead of clflush _cbmem_top_ptr itself.
Fix that by providing the correct address to clflush.
Change-Id: If74591e7753cd9c3c097516430a212d416f53e4d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The headers added are generated as per FSP v2471_02.
Previous FSP version was v2422_01.
Changes Include:
- UPDs description update in FspsUpd.h
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
BUG=b:208336249
BRANCH=None
TEST=Build and boot brya
Change-Id: I4d04652c06a1c1823d3859be209710c273a2ae8c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Device 4 was introduced with a wrong name, since it is the SA Thermal
Subsystem and it does nothing have to do with DSP. Thus, rename it
accordingly.
Change-Id: I8edc764413df5f323098e60d0a3f0f87a7e656cb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60049
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch includes (edk2/edk2-stable202111) all required
headers for edk2-stable202111 EDK2 tag from EDK2 github
project using below command:
>> git clone -b edk2-stable202111 https://github.com/tianocore/edk2.git
commit hash: bb1bba3d776733c41dbfa2d1dc0fe234819a79f2
Only include necessary header files.
MdePkg/Include/Base.h was updated to avoid compilation errors
through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE.
Note: edk2-stable202111 tag is required to adopt FSP 2.3 specification.
- Need to add ExtendedImageRevision in FSP_INFO_HEADER structure.
- Need to add FSP_NON_VOLATILE_STORAGE_HOB2 header.
Change-Id: I786cc05f9a638ac6226ebc8c0eaf1dc8189a4ca4
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This patch adds a new way of implementing flash access for libpayload.
Until now all reads had to be performed using cbfs_media, which is
obsolete. From now on all reads should be performed using
boot_device_read().
This patch also provides a default implementation of boot_device_read()
for x86 architecture.
Change-Id: I1babd2a8414ed9de3ca49903fcb4f036997b5ff3
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI
table), PLD is added to ACPI table. It causes the DUT to not boot into
the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2
to solve this issue.
Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table")
BUG=b:209723556
BRANCH=none
TEST=build coreboot and boot into OS.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ia4cf2d735de524ae721800600536923d1d47f04b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The `cpu_get_power_max()` function returns the TDP in milliwatts, but
the vr_config code interprets the value in watts. Divide the value by
1000 to fix this.
This also fixes an integer overflow when `cpu_get_power_max()` returns
a value greater than 65535 (UINT16_MAX).
Change-Id: Ibe9e0db6762eee5cc363f8b371c8538eb92f6308
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Enable TPM init in bootblock so that all further stages and other CBFS
files are directly measured into PCRs immediately instead of being
logged into a buffer and replayed to the TPM in ramstage.
Change-Id: Ib3ac29aa72abe8e967660ae7e8416aeb8812de26
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
coreboot code currently supports different UDK binding as per
underlying FSP requirement, example: ICL and TGL uses
UDK_2017_BINDING while ADL uses UDK_202005_BINDING Kconfig.
These UDK binding Kconfigs are being used to choose the correct
UDK_VERSION.
This patch introduces `UDK_BASE` Kconfig option so UDK_VERSION
if clause don't need to add specific UDK binding Kconfig everytime with
introduction of newer UDK bindings in future.
Tested with BUILD_TIMELESS=1, Hatch remains identical.
Change-Id: I64c51aa06a14f0ce541537363870ac3925b79a68
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7
SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4
PCH devices are connected on the platform, an external differential
buffer chip needs to be placed at the platform level.
A mainboard designer can choose to add an external clock chip, and
select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER.
CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to
discrete buffer for further distribution to platform.
TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot.
localhost ~ # dmesg | grep mmc
[ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA
[ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa
[ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB
[ 5.494268] mmcblk0: p1
Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CB:58374 (for mb/google/brya0) was merged before brya4es is
available (CB:59728). And since brya4es is forked from brya0, brya0's
change need to be brought into brya4es as well.
BUG=b:203014972
TEST=build
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I97489343b8f7a5b9457cd6f4a61cc37cd10ab450
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`.
The following mainboards enable the DPTF device in the devicetree
despite `Device4Enable` is not being set.
* google/deltaur
Thus, set it to off to keep the current state unchanged.
Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Hook up `SmbusEnable` FSP setting to devicetree state and drop its
redundant devicetree setting `SmbusEnable`.
The following mainboards enable the SMBus device in the devicetree
despite `SmbusEnable` is not being set.
* google/deltaur
* starlabs/laptop
Thus, set it to off to keep the current state unchanged.
Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The original change was for mb/google/redrix (commit 0167f5adbb),
"The ChromeOS kernel platform driver is adding support for a ChromeOS
privacy screen device, and in order to locate that device, the driver
uses the GOOG0010 reserved HID for this"
But it was merged before redrix4es is available. As redrix4es is forked
from redrix, relevant change in redrix need to be brought into
redrix4es as well.
BUG=b:206850071
TEST=build
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I5ac90c249273bf4e75cccb5889844a7f196f56fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CONFIG_ONBOARD_SAMSUMG_MEM was used to force Samsung memory.
CPLD is used to determine the memory type leaving CONFIG_ONBOARD_SAMSUNG_MEM unused.
Remove this config.
BUG = N/A
TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4
Change-Id: I60626552f2e2338cf5cbaaf4dca1b1eb2756d8df
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59755
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CONFIG_ONBOARD_SAMSUMG_MEM was used to force Samsung memory.
CPLD returns different values for every board revision. Use this value
to determine the memory type.
BUG = N/A
TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4
Change-Id: I21b5ddc430410a1e8b3e9012d0c07d278880ff47
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move the SMM Kconfig options to the specific agesa cpu families.
Select NO_SMM for family14 since since no Fam14h platform uses SMM.
Leave SMM_ASEG enabled for family15tn and family16kb for now.
TEST=Boot Debian 11 on PC Engines apu1
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: I09bbe036a88dada847219606ec79c68e7ca8e5cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
All SPI interface setup related functionality that Stoneyridge
implemented in its southbridge code is already present in the common AMD
SoC code, so use that code instead.
The common fch_spi_early_init function requires the SPI controller's
base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right
before it. fch_spi_early_init then calls lpc_enable_spi_rom and
lpc_enable_spi_prefetch which can be removed from the board code now.
Next it calls fch_spi_configure_4dw_burst which does the same as the now
removed sb_disable_4dw_burst function when
SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default.
This option can also only be set to y for SoCs that aren't Stoneyridge.
Finally fch_spi_early_init calls fch_spi_config_modes which configures
the SPI mode and speed settings according to the Kconfig settings and
the settings in the amdfw part. On Kahlee this was done by calls to
sb_read_mode and sb_set_spi100 before. The previous patch added the
remaining Kconfig settings, so the resulting register values don't
change in the non-EM100 case. In the EM100 case the TPM speed is changed
from 64 to 16 MHz.
TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode
with a first-generation EM100 results in Google/Barla reaching the
payload and the show_spi_speeds_and_modes call in bootblock prints the
expected settings:
relevant bootblock console output in non-EM100 case:
SPI normal read speed: 33.33 MHz
SPI fast read speed: 66.66 Mhz
SPI alt read speed: 66.66 Mhz
SPI TPM read speed: 66.66 Mhz
SPI100: Enabled
SPI Read Mode: Dual IO (1-2-2)
relevant bootblock console output in EM100 case:
SPI normal read speed: 16.66 MHz
SPI fast read speed: 16.66 MHz
SPI alt read speed: 16.66 MHz
SPI TPM read speed: 16.66 MHz
SPI100: Enabled
SPI Read Mode: Normal Read (up to 33M)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
