aeffa86cc5
src/device: Don't die() on vBIOS errors
...
Systems can boot to the OS without a display. Don't kill the boot
process based on a vBIOS error, instead just display a warning.
If the issue is actually fatal for some reason, it's going to die
at some point anyway.
BUG=b:175843172
TEST=Boot morphius to OS without a display
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org >
Change-Id: I7d261321cdbe423dd754f6a354e5f50b53563fcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-01-27 10:24:44 +00:00
656743fb6b
soc/amd/common: Notify SMU of AC/DC state upon resume
...
As a result of S3 resume, call ALIB function 1 to report the current
AC/DC state.
BUG=177377069
TEST=Verify printf is called during resume on Morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Change-Id: I3e52b0625c1222f10ea27568d5431328131a26a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-27 10:24:36 +00:00
022c62a7a4
mb/clevo: Drop redundant select HAVE_SMI_HANDLER
...
Already selected from SoC Kconfig.
Change-Id: I131f435ab0a30e33a70773a99c60284f8b9c82c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2021-01-27 10:24:32 +00:00
68a1cb58c0
soc/amd/common/block/smbus: remove stale comment
...
The comment doesn't apply to Stoneyridge, Picasso and Cezanne which are
the only SoCs selecting SOC_AMD_COMMON_BLOCK_SMBUS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I9024de9d3731a0bc64365f959142bf657a53e193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2021-01-27 00:29:01 +00:00
c81509c71d
MAINTAINERS: Add myself to MAINTAINERS
...
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: If82d384eb59ed2f879175dbc7b01e11198877d97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-26 22:22:21 +00:00
4d088699f8
mb/kontron/ktqm77: Convert to ASL 2.0 syntax
...
Change-Id: I7ba4625075fd3c27092d854903baf140521c8f7b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 21:04:09 +00:00
4c77a8b3ed
mb/asus/a88xm-e: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' files are identical.
Change-Id: I8887b869e9ed809f7861b810c2fb994fa2ee062e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 21:00:09 +00:00
19a0923ca9
mb/asus/f2a85-m: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' are identical.
Change-Id: I3a5ef0987f2e03e07f1de2b3b10d65dde3827c70
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 21:00:00 +00:00
76eaab0fd9
mb/asus/am1i-a: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' are identical.
Change-Id: I856494c634c8c932faa7840b0fd0a35663f4de57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46157
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 20:59:51 +00:00
e404eb2aba
mb/bap/ode_e20XX: Convert to ASL 2.0 syntax
...
Change-Id: I07705aed2f41cd0d2a7f4b980046995f44395f07
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:59:23 +00:00
ef7ea6b77f
mb/asus/p2b: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' files are identical.
Change-Id: Ib07e4147f7f1b90f721be147d48ed12ae793c4fd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46159
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 20:58:49 +00:00
78b05575bf
mb/lenovo/t60: Convert *.asl to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' files are identical.
Change-Id: Iea2c0600d696f9da6774affdc33d9c50d5cf2c95
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:57:23 +00:00
0200143db6
mb/kontron/986lcd-m: Convert *.asl to ASL 2.0 syntax
...
Change-Id: I2ef51c0348e76cb34e118ed207de88cc753f8fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:56:53 +00:00
a12c15907f
mb/gigabyte/ga-945gcm-s2l: Convert *.asl to ASL 2.0 syntax
...
Generated 'Build/dsdt.dsl' are identical.
Change-Id: Ic01ca9b58fe948fe5ffbc9e80ea4bae91fb6d581
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:56:36 +00:00
d70c560a19
mb/msi/ms7721: Convert to ASL 2.0 syntax
...
Generated build/dsdt.dsl files are same.
Change-Id: Iaf26af76935dc8cd9642f047e833f0e8b14e6931
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46209
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 20:56:16 +00:00
53dd00a6b0
mb/roda/rk9: Convert to ASL 2.0 syntax
...
Generated build/dsdt.dsl are identical.
Change-Id: I3cfa9d3a199a33ac8faddf4dbc1eed0df8703835
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:55:41 +00:00
f3985488ff
mb/roda/rv11: Convert to ASL 2.0 syntax
...
Generated build/dsdt.dsl files are identical.
Change-Id: Id12c20dbe949c4badfe07578c6d202cd4cfb8191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46211
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 20:54:31 +00:00
24130ec42c
mb/google/stout: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' files are identical.
Change-Id: I1ceb2abdd2562c145b01db7307d817c858d6b978
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:54:08 +00:00
6c78420bcb
soc/intel/braswell/romstage/romstage.c: Use __func__
...
Change-Id: I07d36fb9b499e64eaba8829073c040792a2fee6e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:52:35 +00:00
f984aecc02
device/pci_device.c: Use __func__
...
Change-Id: Ia6c7de99164682dcbcc375969403d2bfb9675f3c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:52:10 +00:00
aded1d7fd0
arch/x86/car.ld: Fix up blob reserved regions
...
Drop duplicated assignment that rewound `.` back, and broke platforms
using MRC.bin and DCACHE_RAM_MRC_VAR_SIZE.
Tested on out-of-tree Acer E5-573 (Broadwell), fixes booting.
Also tested on Asrock B85M Pro4 (Haswell), also fixes booting.
Change-Id: I3f0153f776c07acf7cf92808b677b118c60507c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49909
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 18:01:16 +00:00
aaa4a0d39e
cpu/intel/common/fsb.c: Add Broadwell CPUID models
...
Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for
both the traditional and ULT variants of Broadwell, because the CPU
driver for Haswell already contains CPUIDs for both Broadwell types.
Without this patch, Broadwell CPUs would hang when trying to print the
first console log message, but only if flashconsole was not enabled.
This was missed in commit f542b7bcefth3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49939
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 17:29:20 +00:00
64d0ad347b
soc/amd: Add an option to select if SOC supports ESPI sub decode
...
Cezanne doesn't have eSPIx00034 register define in PPR. Currently only
Picasso need this option.
Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-26 15:51:36 +00:00
56868b8045
mb/google/brya: Add memory DQ map
...
Add memory DQ map based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com >
Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48446
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 10:38:49 +00:00
3ebfd3fb1c
mb/google/zork/Kconfig.name: remove double space in board variant names
...
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: If0bc153cd3a3391b1607848436f0ab5fcd54ce7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-26 10:37:27 +00:00
38cb7c1615
mb/ocp/deltalake: Replace space with underscore in Locator string
...
Per Facebook BIOS requirements 'Locator' field should not
have any space between words.
Tested=On OCP Delta Lake, dmidecode -t 17 to verify.
Change-Id: I2f6f1b2590c55d6da4ca32aef2f50eb332f441dc
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-26 10:37:10 +00:00
1f7a39eaf6
mb/google/volteer/var/voema: Add camera ACPI configuration
...
Add camera ACPI configuration for Voema
BUG=b:169551066
TEST=Build and boot Voema. Start camera app and able to
capture images.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Change-Id: I903e5e0b5f85718c7c9cbb6d5cafb8fc9ad5814e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Jim Lai <jim.lai@intel.com >
2021-01-26 10:36:49 +00:00
05a480acea
ocp/deltalake: Set C-State config
...
Set the supported C-State to C1 and C6. This matches the states in
CPUID(5).
Change-Id: If32b8256097b5b2bee7fb074fab105e4b54d14b3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49803
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 10:35:04 +00:00
31ed8856f9
soc/intel/xeon_sp/acpi.c: Add ACPI C-State table
...
Add the soc ACPI _CST table.
The table may be customized to support the different state
combinations and set by the mainboard config.
Tested on deltalake with acpi_idle driver.
Note, intel_idle may not use ACPI _CST table.
Change-Id: I359daa9556edbe263ab0a7f1849c96c8fe1a0da0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
2021-01-26 10:34:56 +00:00
08de06ad6d
soc/intel: Move c-state resource define
...
De-duplicate the MWAIT_RES define. Move it to intel/common/block.
Change-Id: I43903e4f02a549f53101e79f6febd42f2e54f98f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49802
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 10:34:52 +00:00
3c18186e76
sb,soc/intel: Refactor power_on_after_fail option
...
It's only necessary to call get_option() with SLP_TYP S5.
Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49251
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 09:14:27 +00:00
22236a580d
cpu/x86/smm: Remove unused APMC for C-state and P-state
...
Change-Id: I7a3a1b63c0ef14b1e24ecce2df66f7970e5eb669
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-26 09:14:15 +00:00
9e591c409a
soc/amd: Refactor some ACPI S3 calls
...
Do not pass ACPI S3 state as a parameter, by locally
calling acpi_is_wakeup_s3() compiler has better chance
for optimizing HAVE_ACPI_RESUME=n case.
Test for acpi_s3_allowed() is already included in the
implementation of acpi_is_wakeup_s3() and is removed
as redunandant.
For ramstage, acpi_is_wakeup_s3() evaluates to
romstage_handoff_if_resume().
Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 00:17:38 +00:00
f9acd37d7f
mb/google/auron: Use get_gpios function
...
Change-Id: I91424a45ae67186987630b7686102f467f57e7ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-25 23:43:40 +00:00
75f6ab35ff
soc/amd/picasso: Change GPIO _HID to AMDI0030
...
This matches the _HID used in the picasso UEFI bios.
BUG=none
BRANCH=zork
TEST=boot linux and verify peripherals still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: Ieb441696cbe67a772632990347c12d1d15cfaf13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-25 23:09:58 +00:00
8ace387090
soc/amd/picasso/acpi: Change I2C _HID to AMDI0010
...
This is the new _HID that was used for Raven. It matches the _HID used
by the picasso UEFI bios.
This does change the fixed clock used by linux from 133 MHz to 150 MHz.
BUG=none
BRANCH=zork
TEST=boot linux and verify touch screen and touchpad still function
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I37fcb4a4f0148f4843d026902d694c03aeed3c3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-25 23:09:38 +00:00
4389bbc55d
soc/amd/picasso/acpi: Change UART _HID to AMDI0020
...
This is the new _HID that was used for Raven. It matches the _HID used
by the picasso UEFI bios.
BUG=none
BRANCH=zork
TEST=boot linux and verify UART still works
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I138cb445c84997f4a4006cbb4f6617dac25a61b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-25 23:09:22 +00:00
e53534eead
soc/intel/denverton_ns: Drop unused pattrs.h
...
Change-Id: I78ff11a56b38c4bc4f4f00115de1af4b73d4448c
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-25 19:32:28 +00:00
a1c247b55d
soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver
...
This change uses the newly added meminit block driver and updates ADL
SoC and mainboard code accordingly.
BUG=b:172978729
Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6
Signed-off-by: Furquan Shaikh <furquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
2021-01-25 19:14:19 +00:00
13d6a4647d
soc/amd/picasso: Use makefile variable to locate UCODE
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Change the hardcoded location of microcode patches to using
FIRMWARE_LOCATION.
Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49734
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-25 17:08:24 +00:00
08bd2077bf
soc/amd/common: Refactor ACPI wake source
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Change-Id: I5cb65e131bf2a35c4305ea971812d9799b964c4d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49837
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-25 17:05:43 +00:00
b0db813523
soc/amd: Refactor ACPI power state and ELOG
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Change-Id: Ib7423c8d80355871393c377ebaffdfe2846d8852
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-25 17:01:12 +00:00
b218c20c00
sb,soc/intel: Remove no-op APMC for C-state and P-state
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Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49250
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-25 10:37:13 +00:00
c1d524b8c6
sb/intel/common: Change some SMI logging
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Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49249
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-25 10:35:46 +00:00
9a1620f4ed
cpu/x86/smm: Use common APMC logging
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Unify the debug messages on raised SMIs.
Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-25 10:35:23 +00:00
5e6e5c11c7
mb/google/dedede/var/drawcia: Add support to handle pen detection
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For board version 6 afterward, it will have external pull-up for
GPP_C12, and remove internal pull-up.
BUG=b:177618684
TEST=emerge-dedede coreboot, check evtest if SW_PEN_INSERTED event
(value:1/0) when insert/eject pen, and eject pen to wake system from s0ix
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com >
Change-Id: I503873afb48384168dcd8a822c7246655898356e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Henry Sun <henrysun@google.com >
2021-01-25 09:11:57 +00:00
8130959d01
mb/google/kukui: Add panel for Katsu
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Declare the following panel for Katsu:
- BOE_TV105WUM_NW0
- STA_2081101QFH032011_53G
BUG=b:176523929
TEST=build Katsu image passed
BRANCH=kukui
Change-Id: I59a02198bc0e13f2760677ae4ea3eb05eb883464
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2021-01-25 09:11:31 +00:00
5e0db41602
mb/google/zork: adjust the eDP panel power sequence
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set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight
on and vary backlight.
BUG=b:171269338
BRANCH=zork
TEST=Build; Verify the UPD was passed to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com >
Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
2021-01-25 09:11:17 +00:00
3ec3cb82f9
soc/amd/picasso: Add UPDs for support eDP power sequence adjust
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Add UPDs for eDP power sequence adjust
all pwr sequence numbers below are in uint of 4ms.
BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com >
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-25 09:11:03 +00:00
27b149c30b
soc/amd/picasso: Add UPDs for support eDP power sequence adjust
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Add UPDs for eDP power sequence adjust.
BUG=b:171954512
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com >
Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
2021-01-25 09:10:51 +00:00
