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Author SHA1 Message Date
Zhongtian Wu
969a2a9a30 mb/google/rex/var/screebo: Update touchpad I2C timing 
Change i2c[3] parameter to meet below timing:
t-HIGH > 600ns;
900ns > Thd:dat > 300ns.

BUG=b:286030723
BRANCH=none
TEST=Test success by EE.

Change-Id: I4b2d958a5a0d41e2cfa1087f5cb94cc83bbb1739
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76169
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-05 12:53:33 +00:00
Subrata Banik
35ef2e5606 mb/google/rex/var/ovis: Set TCC to 100°C 
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature for ovis.

BUG=b:270664854
TEST=Build and boot google/ovis.

Change-Id: I0ef626f6cc460f1b460297804b97038705efaf4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-07-05 10:36:33 +00:00
Sumeet Pawnikar
6ce1391d1c soc/intel/meteorlake: add power limits for 28W SKU 
Add power limit values for Meteor Lake 28W SKU.

Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982

BRANCH=None
BUG=b:289854108
TEST=Build FW

Change-Id: I0b4741185278913d11d902d53345ae8ccebb18f8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76239
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-07-05 10:36:09 +00:00
Sumeet Pawnikar
33c6171bde soc/intel/meteoerlake: add support for 28W SKU 
Add power limits support for 28W SKU.

BRANCH=None
BUG=b:289854108
TEST=Build FW

Change-Id: I83deb1e574990cb70f9aac5d5eb46fbb710a6170
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76238
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-05 10:35:57 +00:00
Subrata Banik
3d4ff8498c mb/google/rex/var/ovis: Add Power Limit for 28W 
This patch adds a power limit for Ovis with 28W Intel Meteor Lake
silicon.

Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982

BUG=b:289854108
TEST=Able to boot google/ovis with power limit being overridden as
appropriate to 28W.

Change-Id: I312c70720fd89261c53d5bd4f45236e829d6c790
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
 2023-07-05 10:35:34 +00:00
Kapil Porwal
8c551cbe72 mb/google/rex: Temporarily disable the crashlog 
Currently, boards with ES2 silicon are unable to boot with crashlog
enabled because crashlog driver is unable to handle invalid data.

Temporarily disable the crashlog to unblock development until the issue
is fixed.

BUG=b:289749310
TEST=Able to boot to the OS on Screebo

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic63cf9cf5bfa2c92d8f2c5b13df2f23dc118b389
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76231
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
 2023-07-05 04:23:14 +00:00
Zhongtian Wu
28d18ade43 mb/google/rex/var/screebo: Update touchscreen I2C timing 
Change i2c[0] parameter to meet touchscreen timing.
Thd:dat > 100ns.

BUG=b:287898252
BRANCH=none
TEST=Test success by EE.

Change-Id: I30e7c87d788f7f144276c45e8475af65f1f132ae
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-07-05 01:55:02 +00:00
Felix Held
c32df9aa16 soc/amd/common/block/acpi/ivrs: use IOMMU PCI register definitions 
Use IOMMU_CAP_BASE_[LO,HI] instead of magic values.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7032d9f032a22649951ef1535f39b918eb8bd539
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-07-04 17:51:26 +00:00
Felix Held
e54e141d6c soc/amd/common/block/iommu: factor out PCI register definitions 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie155cab1f659e9f7b64cd87ba8a77260056656d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76222
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-04 17:50:50 +00:00
Sergii Dmytruk
6da62684de util/cbmem: add parsing of TPM logs per specs 
CBMEM can contain log in different forms (at most one is present):
 - coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as
   LB_TAG_TPM_CB_LOG)
 - TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG)
 - TPM2 format (CBMEM_ID_TPM2_TCG_LOG)

The last two follow specifications by Trusted Computing Group, but until
now cbmem couldn't print them.  These formats were added not so long ago
in:
 - commit 4191dbf0c9 ("security/tpm: add TPM log format as per 1.2
   spec")
 - commit 53db677586 ("security/tpm: add TPM log format as per 2.0
   spec")

These changes make cbmem utility check for existence of TPM1.2/TPM2 logs
in CBMEM and add code necessary for parsing and printing of their
entries.

TEST=`cbmem -L` for CONFIG_TPM1=y case
TCPA log:
	Specification: 1.21
	Platform class: PC Client
TCPA log entry 1:
	PCR: 2
	Event type: Action
	Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e
	Event data: FMAP: FMAP

TEST=`cbmem -L` for CONFIG_TPM2=y case
TPM2 log:
	Specification: 2.00
	Platform class: PC Client
TPM2 log entry 1:
	PCR: 2
	Event type: Action
	Digests:
		 SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c
	Event data: FMAP: FMAP

Change-Id: Ib76dc7dec56dd1789a219539a1ac05a958f47a5c
Ticket: https://ticket.coreboot.org/issues/425
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68749
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-04 13:07:13 +00:00
Yu-Ping Wu
6d169aabbd arch/arm64/Makefile.inc: Fix Kconfig name in comment 
Change-Id: I93860a20a425c833b41e16347722e9a879f83ab1
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-07-04 02:41:25 +00:00
Uday M Bhat
68e3826071 mb/google/rex: Enable Bluetooth offload for soundwire audio 
This patch enables BT offload feature for soundwire audio over SSP1.

BT mode is selected via FW_CONFIG and corresponding VGPIOs are
programmed.

BUG=b:275538390
TEST=build and verify BT offload on rex soundwire audio

Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3
Signed-off-by: Uday M Bhat <uday.m.bhat@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75924
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-07-04 00:51:47 +00:00
Dtrain Hsu
eebf63c0c3 mb/google/nissa/var/uldren: Update DPTF parameters and tcc_offset 
Follow the Project_Uldren_Thermal_paramters_list_2023_0626.xlsx to
modify DPTF parameters and tcc_offset.
- Set tcc_offset to 3.
- Update Critical Policy trip point.
- Update Power Limits PL1 minimum step size to control limits (in mW).

BUG=b:282598257
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and pass thermal test.

Change-Id: Ic5bbb3aa3b036a1eae8a95f63b570db2dc6da978
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76105
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
 2023-07-04 00:16:56 +00:00
Mark Hsieh
5c10eaf8c2 mb/google/nissa/var/joxer: Disable external fivr 
In next phase, joxer will remove external fivr.

BUG=b:285477026
TEST=emerge-nissa coreboot and boot to OS, suspend/resume
work normally.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I7fd7ad90e1544966170df402243604379f5790db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
 2023-07-04 00:16:43 +00:00
Eric Lai
b526d0e934 soc/amd/common/block/uart: remove DRIVERS_UART_8250MEM 
Select DRIVERS_UART_8250MEM_32 will select DRIVERS_UART_8250MEM too.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I87a47e2d76ab7a0717edf725bf94d87f9f2357f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76184
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2023-07-04 00:15:42 +00:00
Arthur Heymans
adb8007515 acpi/acpi.c: Move ACPI header creation to a function 
This reduces boilerplate. One functional difference is that SSDT no
longer has oem_revision set to 42.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Id2e54d61970294e028a61ba86c07c5482784e307
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2023-07-03 22:05:03 +00:00
Arthur Heymans
01af0f8ac8 acpi/acpi.c: Reduce boilerplate 
Adding tables to R/XSDT, aligning current pointer, computing checksum is
a lot of boilerplate that needs to be done for each table.

TESTED on foxconn/g41.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2023-07-03 22:03:06 +00:00
Fred Reitberger
5b9957be0a soc/amd/phoenix/Kconfig: Select VBOOT_X86_SHA256_ACCELERATION 
Phoenix is an x86 soc that supports sha256 instructions.

TEST=boot birman to chromeos

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id228399ba02708b97110d524ce12c2626588762d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76166
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
 2023-07-03 13:41:51 +00:00
Fred Reitberger
559f3d49ad soc/amd/phoenix: Remove TODO after review 
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ifd2b53ff24776238190eb946db7b12827fcfc804
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
 2023-07-03 13:35:15 +00:00
Fred Reitberger
865180d681 drivers/spi_flash: Always exit 4-byte address mode when memory-mapped 
Always send the Exit 4-Byte Address Mode (E9h) command before the first
access to the SPI flash in all stages when the SPI flash is
memory-mapped.  This is useful for x86 mainboards that do not access SPI
flash in bootblock yet still need to exit 4-byte addressing mode in
romstage or ramstage.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2023-07-03 13:34:01 +00:00
Jakub Czapiga
00d71ffca8 util/sconfig: Improve usage and long options 
Move usage function closer to main(), remove excessive printf() calls,
use descriptive argument flags.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If5252de63692c5e43bfbde4d7d93e1d7a84e8dff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2023-07-03 13:00:19 +00:00
Kyösti Mälkki
e01742bf3d cpu/x86: Reduce scope of MTRR functions used locally 
Change-Id: Ic00358ee5b05d011a95d85ec355adef71c39a529
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76193
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:59:23 +00:00
Tim Crawford
56c09fb5fd mb/system76/{adl,tgl}: Add FMD files 
Replace `CBFS_SIZE` with FMD files to declare regions and sizes. This
will be used to lock BIOS region (except SMMSTORE) on boot.

`CBFS_SIZE` was incorrectly set to 10 MiB, so this also corrects the
BIOS region size to match the FIT values.

Change-Id: I0f068f4d9b376f12b46faa5bb0c6a08e6cb744d8
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76155
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
 2023-07-03 12:58:43 +00:00
Tim Crawford
10d2af04e7 mb/system76: Add space for ramtop in CMOS layout 
Fixes building when `USE_OPTION_TABLE` is selected.

Change-Id: I4fb017aa549b24eda6b9e0356bc1776d4044c95d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
 2023-07-03 12:58:11 +00:00
Tim Crawford
2f862d3bf4 mb/system76: Select CBFS SMBIOS hooks 
Multiple users have requested to have the DMI values for product UUID
and serial number be populated. Enable the drivers so that we may set
them when flashing or updating firmware.

Change-Id: I710363d9df626d51756a265f0099f26ef28411c2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
 2023-07-03 12:57:30 +00:00
Tim Crawford
8192fa1fa3 mb/system76: Select TPM read delay on all boards 
The Infineon chip occasionally fails Startup or Resume. Adding the
delay makes it work more reliably.

Change-Id: I4a8f98633154888e2167a3d55192b86e13ffcb62
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76095
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:57:03 +00:00
Tim Crawford
482789b015 mb/system76/adl: Remove PL4 values 
System76 EC since system76/ec@99dfbeaec3 sets PL4 values through PECI
based on AC state for all boards. Remove the static PL4 values from
coreboot since they won't be used.

Ref: https://github.com/system76/ec/pull/353
Change-Id: I66bc547ef1b3419fc677fcbdd5ba5d8cc8e14189
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75333
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:56:48 +00:00
Tim Crawford
8e8a2b496e ec/system76/ec: Do not call reset on wake 
Resetting the device will cause the keyboard backlight and airplane LED
to lose their state.

Change-Id: I2f46542fb6b32c479b01335149c9190f6fa1421f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75275
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:56:14 +00:00
Jeremy Soller
6cb18a5b34 mb/system76/rpl: Add Oryx Pro 11 as a variant 
The Oryx Pro 11 (oryp11) is a Raptor Lake-H board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots
- Both M.2 NVMe SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7

Change-Id: I0d29e03cdde523a95ae6d174a9948f4c119cca6e
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:54:25 +00:00
Jeremy Soller
bfb35f2488 mb/system76/tgl-u: Enable reporting CPU C10 state over eSPI 
This allows the EC to detect C10 using eSPI instead of a dedicated pin.

Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:53:30 +00:00
Jeremy Soller
976e09b021 mb/system76/adl: Add Gazelle 17 as a variant 
The gaze17 comes in 2 variants due to differences in the discrete GPU
and network controller used.

- NVIDIA RTX 3050, using Realtek Ethernet Controller
- NVIDIA RTX 3060, using onboard I219-V Ethernet Controller

Tested with a custom TianoCore UefiPayloadPkg payload.

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe SSD
- M.2 SATA SSD
- MicroSD card reader
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S0ix suspend/resume
- Booting to Pop!_OS Linux 22.04 with kernel 6.2.6
- Internal flashing with flashrom v1.2-703-g76118a7c10ed

Not working:

- Discrete/Hybrid graphics: Requires NVIDIA driver
- mDP/HDMI displays on 3060 variant: Requires NVIDIA driver
- Detection of devices in TBT slot on boot
- S3 suspend: MP init eventually fails

Not tested:

- Thunderbolt devices

Change-Id: Ib12ac47e8f34004f72e6234039823530511baea7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:53:12 +00:00
Tim Crawford
46b63bb033 mb/system76/tgl-h: Disable D3cold 
Disable D3cold to prevent issues with Thunderbolt not working after S3
suspend.

Change-Id: Ib4362783546aa01f0f8f5baaad817ee76be9c39c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
 2023-07-03 12:52:32 +00:00
Matt DeVillier
163dbddfe9 soc/amd/*: Utilize get_fmap_value() Makefile function where possible 
Replace:
$(shell awk '$$2 == "xyz" {print $$3}' $(obj)/fmap_config.h)
with:
$(call get_fmap_value,xyz)

to improve code readability/maintainability.

Change-Id: If6859108c7d5611a63fc38909dc75195bfb1d59a
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76168
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2023-07-03 12:51:44 +00:00
Matt DeVillier
2f707374d0 Makefile.inc: relocate get_fmap_value() here from soc/intel/common/block/cse 
Move this function to the root Makefile.inc since other Makefiles use
the exact same function call. Will allow for deduplication in AMD SoC
Makefiles in a follow-on commit.

Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76167
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:50:49 +00:00
Leo Chou
71815c8434 mb/google/nissa/var/pujjo: Tune SX9324 register for pujjoteen5 
Update SX9324 register settings based on tuning value from SEMTECH.

BUG=b:279510275
TEST=Check i2c register settings on Pujjoteen5 and confirm P sensor function can work.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Idc9a2dc817e027551e209c0a26eeebad398f710c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75900
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:49:53 +00:00
Jan Samek
fc8ad3739b mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0 
It's been decided not to use any of the USB 3.0 ports on this board.

This patch disables the remaining USB 3.0 port 0, after the port 1
has already been disabled in commit d0627c7595
("mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1").

BUG=none
TEST=None of the USB 3.0 ports functional anymore after boot,
the USB 2.0 ports continue working.

Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75836
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:49:33 +00:00
Mario Scheithauer
fef762f613 mb/siemens/mc_apl1: Fix wrong register masking 
With the previous instruction the complete register was set to '0'.
Correctly, only the bits 23:16 must be masked.

Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76177
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
 2023-07-03 12:49:09 +00:00
Mario Scheithauer
15e1d97463 mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 
Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3. The appropriate value of
0.7 V was determined by using an oscilloscope.

Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-07-03 12:48:33 +00:00
Mario Scheithauer
b34576b03b mb/siemens/mc_apl1: Rename macro 'TX_DWORD3' to 'TX_DWORD3_P1' 
The offset '0xa8c' for the High Speed I/O Transmit Control Register 3
refers to SATA port 1 only. To make this clear, change the name of the
define from 'TX_DWORD3' to 'TX_DWORD3_P1'.

Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76174
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
 2023-07-03 12:48:05 +00:00
Mario Scheithauer
dfdb5a05b4 mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 macro 
A correction of Tx signal from SATA interface is not necessary on these
boards currently. Therefore remove the define and the corresponding code
on mc_apl5.

Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-07-03 12:47:45 +00:00
Mark Hsieh
19fc004e9a mb/google/nissa/var/joxer: support for different WiFi SAR tables 
Set the WIFI_SAR_ID field in FW_CONFIG to selcet the correct SAR table.

BUG=b:285477026
TEST=emerge-nissa coreboot and check the SAR value

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ibea62c77ecad9b2c475452b706779e4cfc6b06d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76144
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 12:46:59 +00:00
Chia-Ling Hou
8c9ec5af53 mb/google/nissa/yaviks: Tune eMMC DLL value for boot issue 
Resolve boot issue by tuning RX HS50 and HS200.

BUG=b:265611305
TEST=Reboot test 2500 times pass

Change-Id: I8a2727dc0ce9dc86c6bfb6d85567afee1734db62
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75812
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
 2023-07-03 12:46:40 +00:00
Rob Barnes
165cbe505a mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI mask 
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.

BUG=b:283245785
BRANCH=firmware-grunt-11031.B
TEST=Observe kernel ec panic handler run when ec panics

Change-Id: I8eeb5c0935d0531c21bcf4cd3d4fd9dc80b54f79
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2023-07-03 12:46:22 +00:00
Caveh Jalali
37f4f64fcd mb/google/rex: Set AUX orientation at SoC to follow cable for kb8010 
This configures the SoC to flip the orientation of the AUX pins to
follow the orientation of the cable when using the kb8010 retimer. This
is necessary when there is no external retimer/mux or the retimer/mux
does not implement the flip. The kb8010 retimer does not support this
feature, so let the SoC do the flip.

BUG=b:267589112
TEST=verified DP-ALT mode works in both cable orientations on rex with
	reworked kb8010 DB by flykt@

Change-Id: Iad093e27617b80f8301008deb00b57fb9b3a48ba
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76137
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-07-03 12:46:02 +00:00
Jon Murphy
ccfef8454e mb/google/kahlee: Enable Secure OS 
Secure OS was disabled on Grunt devices since it isn't used.
This reduces the attack surface and is meant to mitigate potential
security risks. However, this prevents users from using an alternate OS.
Enable Secure OS upstream to allows users to use Windows, and ensure
that it is still disabled in the chromium repo.

BUG=b:287630343
TEST=Builds with Secure OS included.
Cq-Depend: chromium:4620881

Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2023-07-03 12:45:33 +00:00
Riku Viitanen
685097ba3b mb/hp: Add new port for compaq_8300_elite_usdt 
New port based on autoport.

Autoport worked with minor tweaks, but fan speeds went almost
immediately to the maximum. They are controlled by the NPCD379
Super I/O which isn't supported by coreboot.

But coreboot already has code for NPCD378,
which HP Compaq 8200 SFF makes use of.

So SuperIO configuration was copied from the 8200 SFF port.
It seems to work without any issues in "normal" use.
Most importantly, fan speed control seems to work correctly.

However this means that some of the SuperIO LDNs may be configured
incorrectly. See the comments on Gerrit for more information.

The following is tested and is working:
* Native raminit with both DIMMs
* Libgfxinit textmode and framebuffer on both DisplayPorts and VGA
* External USB2 and USB3 ports: they all work
* USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports)
* Ethernet
* Mini-PCIe WLAN
* SATA: 2.5" SSD and optical drive bay
* Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1
* GRUB (with Libreboot config)
* PS/2 keyboard and mouse
* S3 suspend and resume, wake using USB keyboard
* Headphone output, line out, internal speaker
* Wake on LAN
* Rebooting
* CMOS options & nvramcui

Untested:
* mSATA slot. The SATA port needs to be enabled on devicetree
  too, but I'm unable to test due to lack of hardware
* Line in, mic input
* MXM graphics card
* EHCI debug

Not working:
* Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so
  maybe it just isn't present
* PS/2 keyboard wake from S3

Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74906
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 05:01:02 +00:00
Sheng-Liang Pan
8d16a14367 mb/google/dedede/var/taranza: Add more USB configuration 
- remove usb2_ports[5] since taranza doesn't have PL2303.
- add usb2_ports[6] and usb3_ports[1] for Type-A Port A4.

BUG=b:288094807, b:278167978
TEST=emerge-dedede coreboot chromeos-bootimage
     verified all the USB port works

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7b411c21271497ba386143140aa8cfbb17a1a111
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76186
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-03 00:40:07 +00:00
Subrata Banik
d44e08ad9f mb/google/rex/var/ovis: Enable LAN0 
This patch performs below operations to enable LAN0.
  - Complete the LAN PEREST power sequencing
  - Program the SRC_CLKREQ (GPP_D20) with correctly.
  - Add overridetree.cb entry to configure the LAN0 device.

BUG=b:289395519
TEST=Able to boot google/ovis with LAN0 being enabled.

Change-Id: I91b0a76395ade4459cf8705c333728a71f95df14
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76213
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-02 22:31:41 +00:00
Subrata Banik
9d8baea15c mb/google/rex/var/ovis: Enable LAN1 
This patch performs below operations to enable LAN1.
  - Add overridetree.cb entry to configure the LAN device.
  - Complete the LAN1/SD PEREST power sequencing

BUG=b:289395519
TEST=Able to boot google/ovis with LAN1 being enabled.

Change-Id: Ifb67cb8e6fc03e3ff14b1b3d8382322fd0b3aeff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76212
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-02 22:31:28 +00:00
Subrata Banik
ad7ead7cbf mb/google/rex/var/ovis: Configure GPP_V12 PAD 
This patch configures GPP_V12 aka SOC_SLP_LAN_L properly as per the
Ovis schematics dated June'23 to ensure LAN port is not in sleep.

BUG=b:289395519
TEST=Able to measure SLP_LAN PIN and confirm it's deasserted.

Change-Id: I1fe8715862823149c8a1f05e3e4463a615fbbbce
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76211
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-07-02 22:30:43 +00:00