5790a05237
soc/intel/meteorlake: Add PMC GPIO GPE group mapping
...
Add two missing mapping for GPIO GPE routes
Signed-off-by: Cliff Huang <cliff.huang@intel.com >
Change-Id: I3f0d13cf7c07201856e934f22efc4cc8c4ea5bf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77423
Reviewed-by: Subrata Banik <subratabanik@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-26 21:08:46 +00:00
668b8ccad3
libpayload: Skip unknown arguments to clang
...
This compiler argument only exists on gcc.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I10902517c86daedc9853e6f6cac8fcf513211bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77436
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-26 21:06:30 +00:00
536ea50c53
libpayload: Remove unnecessary brackets
...
This fixes compilation with clang.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I675056c8a15fe446bba81a144bfea64d106df293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77435
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-26 21:05:54 +00:00
ae57f1d2dc
libpayload: Fix untyped function arguments
...
This is necessary with clang.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: Icc197fbd48b49bfa8770caf01727669b0ac59090
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2023-08-26 21:01:43 +00:00
aacf35cca3
docs: Tidy up the English in the testing tutorial
...
Tweak a few sentences noticed when reading this.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0a072c83402bc551a6bbdb7cd7c55fc3505784b2
Signed-off-by: Simon Glass <sjg@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77464
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Reviewed-by: Patrick Georgi <patrick@coreboot.org >
Tested-by: Patrick Georgi <patrick@coreboot.org >
2023-08-26 20:57:37 +00:00
d7c88c2308
docs: Mention add_intermediate and provide an example
...
This is a useful feature, so add a note about it.
Change-Id: If29f6480f878bdaf877dc208cc4861b884e10840
Signed-off-by: Simon Glass <sjg@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <patrick@coreboot.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77465
Tested-by: Patrick Georgi <patrick@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-08-26 20:57:11 +00:00
f40f4a6e23
payloads/U-Boot: Use github mirror and latest version
...
Update the U-Boot version to the latest release. Also switch to github
since it is typically much faster to download than the existing URL.
Drop the 'experimental' tag since this payload is pretty stable. It is
also tested regularly in U-Boot's CI.
Change-Id: I082130539c3474593a82e4b21cb995380f4db168
Signed-off-by: Simon Glass <sjg@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77149
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77463
Reviewed-by: Patrick Georgi <patrick@coreboot.org >
Tested-by: Patrick Georgi <patrick@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2023-08-26 20:56:10 +00:00
b2893e22e6
memrange: Honor limit in the last step of top-down stealing
...
We only checked that the resource fits below the given `limit` in
memranges_find_entry(), but then accidentally placed it at the top
of the found memrange. As most resources have only a coarse limit,
e.g. the 4G barrier of 32-bit space, this became only visible when
artificially setting an unusual, lower limit on a resource.
So, for the final placement, use `MIN(limit, range end)` instead
of the range's end alone.
Change-Id: I3cc62ac3d427683c00ba0ac9f991fca62e99ce44
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-08-26 20:29:37 +00:00
8a58483072
mb/google/brask/var/kuldax: Set customized_leds value for RTL8111K
...
Set customized_leds value for RTL8111K to fix led can't work.
BUG=b:297093096
BRANCH=firmware-brya-14505.B
TEST=Verified RTL8125 and RTL8111K led can work normally.
Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-25 14:41:30 +00:00
c61be60b97
mb/google/brya: Create nokris variant
...
Create the nokris variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:285838647
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_NOKRIS
Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Derek Huang <derekhuang@google.com >
2023-08-25 14:41:06 +00:00
93be5d5d07
util/cbfstool: Add eventlog support for PSR data backup status
...
In order to support logging of events for PSR data backup command
status during CSE firmware downgrade, add support for
ELOG_TYPE_PSR_DATA_BACKUP and ELOG_TYPE_PSR_DATA_LOST types.
BRANCH=None
BUG=b:273207144
TEST=Verify event shows in eventlog after CSE firmware downgrade
Change-Id: Ibb78ac8d420bb7a64328ce009ddcb99030519ec6
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com >
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77005
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com >
2023-08-25 14:40:40 +00:00
055b874658
commonlib: Add PSR backup eventlog types
...
Add new eventlog types to support logging of Platform Service Record
(PSR) backup related messages. Eventlog entries are added on PSR data
backup success/failure and also when PSR data is lost.
BRANCH=None
BUG=b:273207144
TEST=Verify elog event added after PSR data backup command is sent
cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent
...
ELOG: Event(B9) added with size 10 at 2023-07-27 06:44:49 UTC
Change-Id: I01ce3f7ea24ff0fdbb7a202ec3c75973b59d4c14
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com >
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77004
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-25 14:39:45 +00:00
1e3138fe0b
mb/google/rex/var/ovis: Update PWM_BUZZER GPIO config
...
BUG=b:271491845
TEST=Build and boot google/ovis on Rex P1 with buzzer added on GPP_B08
Change-Id: I44718ea15c93a075b6468f335a869a2cfa585273
Signed-off-by: Jakub Czapiga <jacz@semihalf.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76049
Reviewed-by: Subrata Banik <subratabanik@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
2023-08-25 14:38:48 +00:00
6319ef9718
soc/intel/apollolake: Correct the logic for the legacy 8254 timer
...
The `use_8254` should be flipped, the same as the other Intel
SOCs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: I2d6c859c0910b796d2ae5874a560ff9974578106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2023-08-25 14:38:31 +00:00
2cd2263c32
mb/google/nissa/var/joxer: set the DB_USB field in FW_CONFIG
...
Joxer will have SKUs with no type-c on daughter board, add fw_config
for EC control it.
BUG=b:297131468
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com >
Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-25 14:37:45 +00:00
80bd3ac5fe
MAINTAINERS: Add Nicholas Chin for coreDOOM payload integration
...
Change-Id: Idd3acd204c0809753b6f5534790e1dc81c10b761
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71859
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-25 13:28:18 +00:00
2c3cded4bc
mb/amd/birman: Enable two USB4 xHCI controller devices
...
TEST: Boot to ubuntu OS and verify that USB4 devices are listed in lspci command
00:08.3/06:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c0
00:08.3/06:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c1
Change-Id: I6253a7694702179454bc1ca14825fd4f3b949c13
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-08-25 12:46:42 +00:00
354a2456ac
payloads/external/LinuxBoot: Fix boot
...
Fix regression introduced in I25e757108e0dd473969fe5a192ad0733f1fe6286
"payloads/external/LinuxBoot: Clean up".
Include the initrd into the payload. Allows to actually use LinuxBoot.
Change-Id: I5ab6b1a43a4100e83f4c188b9ea3451ab7b4ffe5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77412
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com >
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-25 12:27:09 +00:00
4ff1d63fc4
soc/amd/common/include/root_complex: add IOHC MISC SMN base addresses
...
The Genoa server SoC has 4 IOHC PCI roots instead of the 1 the mobile
SoCs have, so add the additional 3 SMN base address definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I72dba39bff7c7a739e1dfddd80e7f22e65b5f139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77395
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-25 12:24:01 +00:00
53a43f14da
drivers/intel/fsp2/Makefile.inc: Deduplicate compression type checks
...
When LZMA compression is selected, then it's not needed to check if LZ4
compression is selected in addition. So instead of handling both cases
separately, check for LZ4 only if LZMA is not selected.
This applies to the cases of both, FSP-M and FSP-S.
Change-Id: I4ea61a38baf4c29bf522a50a26c6b47292e67960
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77323
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-08-25 10:03:20 +00:00
fa17a9d03c
mb/google/rex/var/karis: Add SOC_TCHSCR_INT settings to gpio table
...
Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage
gpio table.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
2023-08-25 03:23:46 +00:00
33a5722bd7
mb/google/rex/var/karis: Fix incorrect GPIO pad numbers
...
Fix incorrect GPIO pad numbers. GPP_F19 was mistakenly used instead of
GPP_F14, GPP_F15 and GPP_F16 GPIOs.
BUG=none
TEST=none
Signed-off-by: Kapil Porwal <kapilporwal@google.com >
Change-Id: I219b78a5e92d9c56799964ea88615c27aed2e92e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77401
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-25 03:23:19 +00:00
bfdefc2f9a
Makefile: Fix typo in make help output
...
Change-Id: I124e7d68198050616795a67df23b6481f6fe1276
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77407
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-24 22:19:07 +00:00
4f014835e1
docs: Redirect top-level make targets to Documentation/
...
To avoid redundancy about how to call into `Makefile.sphinx`,
only do that from the `Documentation/Makefile` and call into
that from the top level.
Change-Id: I99c462cdaf83d711e4b7c07b713d304274db8cb4
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Simon Glass <sjg@chromium.org >
2023-08-24 22:18:52 +00:00
1312ef49b3
Kconfig: Add option to make clang the default compiler
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: Ie910f654abdb8d79c686363d2bd8af4ceeea4087
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76436
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-24 22:08:59 +00:00
1f9eadabbb
docs/mb: update hp/compaq_elite_8300_usdt docs
...
- Internal flashing possible
- Fix link
- Link here from the list of mainboards
- More consistent naming
Change-Id: Iaf6448c1e9f0dae9480fa9785a12f09d42f8cf7d
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77377
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-24 22:07:33 +00:00
f442eadcad
mb/hp/compaq_elite_8300_usdt: enable mSATA
...
Tested with a Kingston UV500.
It works the same (3Gb/s) as with vendor FW.
According to smartctl -a /dev/sda:
SATA Version is: SATA 3.1, 6.0 Gb/s (current: 3.0 Gb/s)
Change-Id: I5c714351586e6084029ce4c54fb47cbae4d3405b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77376
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
2023-08-24 22:07:14 +00:00
6117a2d296
mb/siemens/fa_ehl: Remove RTC RV3028C7
...
Delete this RTC from the configuration as fa_ehl mainboard
uses a different real time clock.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com >
Change-Id: Ifd6b68d05a094cb4c890f1ffce62d89b771e23c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jan Samek <jan.samek@siemens.com >
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com >
2023-08-24 14:03:05 +00:00
7f99551d5c
mb/siemens/fa_ehl: Remove TPM
...
The mainboard currently does not make use of a dedicated TPM.
Although it has one assembled. This TPM is not connected
via LPC hence it is turned off in the devicetree.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com >
Change-Id: I96cc38c3812d76d654339ad5b2b7f88fd1327779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77351
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jan Samek <jan.samek@siemens.com >
2023-08-24 14:02:45 +00:00
a9d8531c8c
mb/siemens/fa_ehl: Remove NC_FPGA
...
fa_ehl mainboard does not make use of the SIEMENS NC_FPGA
as it is not placed on this board.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com >
Change-Id: I5f1f796e4339ba37d461d6818c2bb6ba028b89c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com >
Reviewed-by: Jan Samek <jan.samek@siemens.com >
2023-08-24 14:02:24 +00:00
b18726da2f
Makefile: Update build for include-what-you-use
...
This patch saves the output of the IWYU build into $(obj)/iwyu.txt. It
will also automatically adds -k to the MAKEFLAFGS when IWYU is selected,
so that the build doesn't halt after the first operation.
When IWYU is not selected, there is no change to the build.
This will allow us to create an automated IWYU build on jenkins.
Signed-off-by: Martin Roth <gaumless@gmail.com >
Change-Id: I0ea300d4c64bb923e9f7cc0e595885c3006ec3ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77192
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2023-08-24 13:58:51 +00:00
00e92f4538
mb/google/dedede/var/boxy: Enable 100M mode blink in RTL8111H LAN LED config
...
Enable bit 9 for 100M mode green LED blink.
Reference:
- RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration
BUG=b:293983804
TEST=emerge-dedede coreboot and verify LAN LED behavior
Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Derek Huang <derekhuang@google.com >
2023-08-24 13:39:49 +00:00
d6c2e054f8
mb/google/nissa/var/yaviks: rename DB_NONE to DB_1A
...
Yaviks doesn't have none DB sku, and rename to DB_1A for yahiko.
BUG=b:294928078, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Icb952c0716d446d5feb5580f357120a27193284e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77384
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-24 13:37:20 +00:00
303a895d77
libpayload: Outsource delay function into own header
...
For libflashrom we need the delay functions but when including the whole
libpayload.h it has conflicting symbols.
Change-Id: I6e4a669b8ba25836fb870d74c200985c1bfdb387
Signed-off-by: Thomas Heijligen <src@posteo.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2023-08-24 13:35:02 +00:00
711f84d177
soc/intel/metorlake: Fix PMC GPIO group assignment
...
Those values need to match with the ones defined in PMC PWRM
GPIO CFG register.
Signed-off-by: Cliff Huang <cliff.huang@intel.com >
Change-Id: I8e84df83caab794e2fe7186e89e78343c2b55fd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-08-24 13:33:50 +00:00
377153d58d
mainboard/siemens/fa_ehl: Add new mainboard based on mc_ehl2
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Add a new mainboard called fa_ehl which is based on Siemens's
'mc_ehl2'. This commit simply copies the mainboard directory and
adjusts the naming to match the new board's name. Moreover a variants
scheme is provided for possible alternative implementations. Follow-up
commits will introduce the needed changes for the new mainboard.
Change-Id: Ia389c8812d14db8b663547e6336e900becbc8be6
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76444
Reviewed-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Jan Samek <jan.samek@siemens.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com >
2023-08-24 13:31:17 +00:00
736d4d25df
acpi: Add function to add ARM PL011 to ACPI DBG2
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I3c3f7f579ec0ec4fdb72e1f6b785026daab17bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76297
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-24 13:20:06 +00:00
06cb997b0a
soc/intel/apollolake: Move the PMC definitions to pmc.h file
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Add a pmc.h file, which is needed for OC watchdog compilation. The PMC
definitions from pm.h are moved to pmc.h.
TEST=Build UP Squared and Intel GLKRVP sucessfully.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Change-Id: I2726aaae1ce60d15a3944dadcf793def2dcb3a1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com >
2023-08-24 12:59:48 +00:00
58a309a8f3
MAINTAINERS: Add Subrata and Nick for google/brya and hatch mbs
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Change-Id: I8308ac1d2f3c9a34b55c788797bccd4e7fcefd5c
Signed-off-by: Subrata Banik <subratabanik@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77348
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
2023-08-24 12:56:24 +00:00
eb6642d8e4
soc/mediatek/mt8188: Remove GPT timer init
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GPT timer init is no longer needed after DRAM blob is switching to ARM
arch timer.
BUG=b:229800119
TEST=boot to kernel
Change-Id: Iec1f93c96e791220feed4225959ef15c074ba577
Signed-off-by: Yidi Lin <yidilin@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77388
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-24 12:55:41 +00:00
c740c65fb9
Update vboot submodule to upstream main
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Updating from commit id 0c11187c:
2023-08-07 11:41:45 +0000 - (vboot_reference: Rename Cr50 to GSC when applicable)
to commit id 24cb127a:
2023-08-22 00:19:10 +0000 - (sign_uefi_unittest.py: Fix long-line lint)
This brings in 24 new commits:
24cb127a sign_uefi_unittest.py: Fix long-line lint
52ac0c71 dump_fmap: Rename format name from 'pretty' to 'parser'
068376d9 dump_fmap: Add description about formats
f67ae949 crossystem: stop supporting legacy chromeos_acpi driver
e6bd72f7 Revert "futility/cmd_vpd: Add vpd listing subcommand"
c7593acc futility: updater: fix build warning 'incompatible function pointer'
394fbfad crossystem: Binary search RW_NVRAM to find the active entry
a5b80353 keygeneration: drop ec_{data,root}_key
1c9b603d futility: updater: Refactor manifest generation
0a4be4a0 futility: updater: Use signer_config for all boards by default
f9d1f0b0 futility: Fix closing file in error path
4dbadfb3 vboot_reference: Remove VB2_RECOVERY_CR50_BOOT_MODE
11bdc1f5 futility: updater: Enable keyset in signer_config based manifest
35e69bcd futility: Change FLMSTR values set by --unlock_me
0ca8212b futility: updater: Use signer_config manifest instead of setvars
0e24a8ef scripts: use new fw updater pack/repack commands
4378179b futility/cmd_vpd: Add vpd listing subcommand
2fc252d8 futility: updater: Remove deprecated Glados platform quirks
3119182d x86/crossystem: Fix snprintf error for hostlib
06a0b9d0 sign_uefi: Remove exception catching
bcfd831e sign_uefi: Clarify comment for removing signatures
4cb7b0e5 crossystem: support new chromeos_acpi driver
eb37f19d vboot: remove trailing newline from sysfs
ec173ee4 vboot: rename ReadFileString() to ReadFileFirstLine()
Change-Id: I6c92791404dc1c6a3efc8bb9046fe5017ba794fb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yidi Lin <yidilin@google.com >
2023-08-24 12:55:11 +00:00
d597320d8e
mb/google/brya/var/vell: Add new GFX devices with custom _PLD
...
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I62103563ec49769cd842fedf8c2c55118c55aa14
Signed-off-by: Won Chung <wonchung@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-08-24 12:54:19 +00:00
4eaa0a929f
mb/google/brya/var/taniks: Add new GFX devices with custom _PLD
...
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I12fa83987869b9a52940a49e9f7897d62abf59ff
Signed-off-by: Won Chung <wonchung@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-08-24 12:54:02 +00:00
020d43e553
mb/google/brya/var/taeko: Add new GFX devices with custom _PLD
...
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I07e85f28c4f260d04317ec594e162db20f3d4ddd
Signed-off-by: Won Chung <wonchung@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-08-24 12:53:50 +00:00
7f5c6d21c6
mb/google/brya/var/volmar: Add new GFX devices with custom _PLD
...
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie7982d1001c4a65322b4e6fdbd70b20c8eee6f0e
Signed-off-by: Won Chung <wonchung@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-08-24 12:53:24 +00:00
d64da18c4a
mb/google/brya/var/primus: Add new GFX devices with custom _PLD
...
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I78eee4c5f11b06fbc104182a4313c20be91b821b
Signed-off-by: Won Chung <wonchung@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76905
Reviewed-by: Subrata Banik <subratabanik@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-24 12:53:08 +00:00
f860d5aba0
mb/google/brya/var/osiris: Add new GFX devices with custom _PLD
...
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b
Signed-off-by: Won Chung <wonchung@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-08-24 12:52:57 +00:00
fb69c56971
mb/google/brya/var/omnigul: Add new GFX devices with custom _PLD
...
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97
Signed-off-by: Won Chung <wonchung@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-08-24 12:52:33 +00:00
939d07ea35
mb/google/brya/var/mithrax: Add new GFX devices with custom _PLD
...
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447
Signed-off-by: Won Chung <wonchung@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-08-24 12:52:14 +00:00
34ce8c7377
mb/google/rex/var/karis: Disable GSPI0
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According to the schematic, karis does not have a SPI touchscreen,
remove related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jakub Czapiga <jacz@semihalf.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
2023-08-24 12:52:08 +00:00
