Elyes HAOUAS
bec78e32d6
src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'
...
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2019-10-21 14:21:09 +00:00
Kyösti Mälkki
540151f115
intel/haswell: Use smm_subregion()
...
Change-Id: Idfb13ab03d4d4ae764bdda62a29848db9d8dcd81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34737
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-28 22:52:47 +00:00
Kyösti Mälkki
cd7a70f487
soc/intel: Use common romstage code
...
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-26 21:08:41 +00:00
Kyösti Mälkki
a963acdcc7
arch/x86: Add <arch/romstage.h>
...
Start with moving all postcar_frame related function
declarations here from <arch/cpu.h>.
Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-22 02:50:35 +00:00
Kyösti Mälkki
544878b563
arch/x86: Add postcar_frame_common_mtrrs()
...
As most platforms will share the subset of enabling
both low RAM WB and high ROM WP MTRRs, provide them
with a single function.
Add possibility for the platform to skip these if
required.
Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-15 05:32:44 +00:00
Kyösti Mälkki
5bc641afeb
cpu/intel: Refactor platform_enter_postcar()
...
There are benefits in placing the postcar_frame structure
in .bss and returning control to romstage_main().
Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2019-08-15 05:31:29 +00:00
Kyösti Mälkki
e2e1f12265
intel/haswell: Move platform_enter_postcar()
...
Do this for consistency with remaining cpu/intel sources.
Also wipe out some spurious includes.
Change-Id: I1adde58966eae9205703b87e7aa17c50e5791a85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-08-11 18:37:19 +00:00
Kyösti Mälkki
fe481eb3e5
northbridge/intel: Rename ram_calc.c to memmap.c
...
Use a name consistent with the more recent soc/intel.
Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-08-07 05:42:15 +00:00
